diff options
| author | Xue Dong <xdong@nvidia.com> | 2013-09-17 16:43:58 -0700 |
|---|---|---|
| committer | Ajay Nandakumar <anandakumarm@nvidia.com> | 2013-10-01 13:40:26 +0530 |
| commit | fd19eb665f45d599c831a568ae28fe365c467465 (patch) | |
| tree | 403a39e88824cc98127c2f9fcc18025089bc7f4a /arch/arm/mach-tegra/board-ardbeg-memory.c | |
| parent | ae49c05acc91c5b7dff31e6d8cc48a695ae0b94c (diff) | |
arm: tegra: update dvfs table add pllc_out entry
Change-Id: I986d261c9a2fc03fcfbce84aec07f281d5721c00
Signed-off-by: Xue Dong <xdong@nvidia.com>
Reviewed-on: http://git-master/r/270380
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>
(cherry picked from commit d2f698c9c653c5098eb5d121038dd362785c8b0e)
Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/board-ardbeg-memory.c')
| -rw-r--r-- | arch/arm/mach-tegra/board-ardbeg-memory.c | 1200 |
1 files changed, 1162 insertions, 38 deletions
diff --git a/arch/arm/mach-tegra/board-ardbeg-memory.c b/arch/arm/mach-tegra/board-ardbeg-memory.c index 61c915e6f217..5e13ee5b7d12 100644 --- a/arch/arm/mach-tegra/board-ardbeg-memory.c +++ b/arch/arm/mach-tegra/board-ardbeg-memory.c @@ -29,9 +29,458 @@ static struct tegra12_emc_table ardbeg_emc_table[] = { { - 0x14, /* V5.0.1 */ + 0x15, /* V5.0.1 */ + "04_40800_0_V5.0.1_V0.3", /* DVFS table version */ + 40800, /* SDRAM frequency */ + 800, /* min voltage */ + 800, /* gpu min voltage */ + "pllp_out0", /* clock source id */ + 0x40000012, /* CLK_SOURCE_EMC */ + 167, /* number of burst_regs */ + 31, /* number of up_down_regs */ + { + 0x00000001, /* EMC_RC */ + 0x0000000a, /* EMC_RFC */ + 0x00000000, /* EMC_RFC_SLR */ + 0x00000001, /* EMC_RAS */ + 0x00000000, /* EMC_RP */ + 0x00000004, /* EMC_R2W */ + 0x0000000a, /* EMC_W2R */ + 0x00000003, /* EMC_R2P */ + 0x0000000b, /* EMC_W2P */ + 0x00000000, /* EMC_RD_RCD */ + 0x00000000, /* EMC_WR_RCD */ + 0x00000003, /* EMC_RRD */ + 0x00000003, /* EMC_REXT */ + 0x00000000, /* EMC_WEXT */ + 0x00000006, /* EMC_WDV */ + 0x00000006, /* EMC_WDV_MASK */ + 0x00000006, /* EMC_QUSE */ + 0x00000002, /* EMC_QUSE_WIDTH */ + 0x00000000, /* EMC_IBDLY */ + 0x00000005, /* EMC_EINPUT */ + 0x00000005, /* EMC_EINPUT_DURATION */ + 0x00010000, /* EMC_PUTERM_EXTRA */ + 0x00000004, /* EMC_PUTERM_WIDTH */ + 0x00000000, /* EMC_PUTERM_ADJ */ + 0x00000000, /* EMC_CDB_CNTL_1 */ + 0x00000000, /* EMC_CDB_CNTL_2 */ + 0x00000000, /* EMC_CDB_CNTL_3 */ + 0x00000004, /* EMC_QRST */ + 0x0000000c, /* EMC_QSAFE */ + 0x0000000d, /* EMC_RDV */ + 0x0000000f, /* EMC_RDV_MASK */ + 0x0000012e, /* EMC_REFRESH */ + 0x00000000, /* EMC_BURST_REFRESH_NUM */ + 0x0000004b, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002, /* EMC_PDEX2WR */ + 0x00000002, /* EMC_PDEX2RD */ + 0x00000001, /* EMC_PCHG2PDEN */ + 0x00000000, /* EMC_ACT2PDEN */ + 0x00000008, /* EMC_AR2PDEN */ + 0x0000000f, /* EMC_RW2PDEN */ + 0x0000000b, /* EMC_TXSR */ + 0x0000000b, /* EMC_TXSRDLL */ + 0x00000004, /* EMC_TCKE */ + 0x00000005, /* EMC_TCKESR */ + 0x00000004, /* EMC_TPD */ + 0x00000000, /* EMC_TFAW */ + 0x00000000, /* EMC_TRPAB */ + 0x00000005, /* EMC_TCLKSTABLE */ + 0x00000005, /* EMC_TCLKSTOP */ + 0x00000138, /* EMC_TREFBW */ + 0x00000000, /* EMC_FBIO_CFG6 */ + 0x00000000, /* EMC_ODT_WRITE */ + 0x00000000, /* EMC_ODT_READ */ + 0x1069aa98, /* EMC_FBIO_CFG5 */ + 0x002c00a0, /* EMC_CFG_DIG_DLL */ + 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000, /* EMC_DLL_XFORM_DQS0 */ + 0x00064000, /* EMC_DLL_XFORM_DQS1 */ + 0x00064000, /* EMC_DLL_XFORM_DQS2 */ + 0x00064000, /* EMC_DLL_XFORM_DQS3 */ + 0x00064000, /* EMC_DLL_XFORM_DQS4 */ + 0x00064000, /* EMC_DLL_XFORM_DQS5 */ + 0x00064000, /* EMC_DLL_XFORM_DQS6 */ + 0x00064000, /* EMC_DLL_XFORM_DQS7 */ + 0x00064000, /* EMC_DLL_XFORM_DQS8 */ + 0x00064000, /* EMC_DLL_XFORM_DQS9 */ + 0x00064000, /* EMC_DLL_XFORM_DQS10 */ + 0x00064000, /* EMC_DLL_XFORM_DQS11 */ + 0x00064000, /* EMC_DLL_XFORM_DQS12 */ + 0x00064000, /* EMC_DLL_XFORM_DQS13 */ + 0x00064000, /* EMC_DLL_XFORM_DQS14 */ + 0x00064000, /* EMC_DLL_XFORM_DQS15 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS15 */ + 0x0007c000, /* EMC_DLL_XFORM_DQ0 */ + 0x0007c000, /* EMC_DLL_XFORM_DQ1 */ + 0x0007c000, /* EMC_DLL_XFORM_DQ2 */ + 0x0007c000, /* EMC_DLL_XFORM_DQ3 */ + 0x00007c00, /* EMC_DLL_XFORM_DQ4 */ + 0x00007c00, /* EMC_DLL_XFORM_DQ5 */ + 0x00007c00, /* EMC_DLL_XFORM_DQ6 */ + 0x00007c00, /* EMC_DLL_XFORM_DQ7 */ + 0x100002a0, /* EMC_XM2CMDPADCTRL */ + 0x00000000, /* EMC_XM2CMDPADCTRL4 */ + 0x00111111, /* EMC_XM2CMDPADCTRL5 */ + 0x0030a11c, /* EMC_XM2DQSPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL3 */ + 0x77ffc085, /* EMC_XM2CLKPADCTRL */ + 0x00000e0e, /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108, /* EMC_XM2COMPPADCTRL */ + 0x07070004, /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee, /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400, /* EMC_XM2DQSPADCTRL3 */ + 0x00514514, /* EMC_XM2DQSPADCTRL4 */ + 0x00514514, /* EMC_XM2DQSPADCTRL5 */ + 0x51451400, /* EMC_XM2DQSPADCTRL6 */ + 0x0505003f, /* EMC_DSR_VTTGEN_DRV */ + 0x00000014, /* EMC_TXDSRVTTGEN */ + 0x00000000, /* EMC_FBIO_SPARE */ + 0x00000000, /* EMC_ZCAL_INTERVAL */ + 0x00000042, /* EMC_ZCAL_WAIT_CNT */ + 0x000e000e, /* EMC_MRS_WAIT_CNT */ + 0x000e000e, /* EMC_MRS_WAIT_CNT2 */ + 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ + 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ + 0xa1430000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_CTT */ + 0x00000004, /* EMC_CTT_DURATION */ + 0x0000f2f3, /* EMC_CFG_PIPE */ + 0x80000364, /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a, /* EMC_QPOP */ + 0xb0000001, /* MC_EMEM_ARB_CFG */ + 0x80000017, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003, /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203, /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402, /* MC_EMEM_ARB_DA_COVERS */ + 0x74c30303, /* MC_EMEM_ARB_MISC0 */ + 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ + }, + { + 0x00000001, /* MC_MLL_MPCORER_PTSA_RATE */ + 0x00000014, /* MC_PTSA_GRANT_DECREMENT */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_XUSB_0 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_XUSB_1 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_TSEC_0 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMCA_0 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMCAA_0 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMC_0 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMCAB_0 */ + 0x00ff0049, /* MC_LATENCY_ALLOWANCE_PPCS_0 */ + 0x00ff0080, /* MC_LATENCY_ALLOWANCE_PPCS_1 */ + 0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORE_0 */ + 0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORELP_0 */ + 0x000800ff, /* MC_LATENCY_ALLOWANCE_HC_0 */ + 0x000000ff, /* MC_LATENCY_ALLOWANCE_HC_1 */ + 0x00ff0004, /* MC_LATENCY_ALLOWANCE_AVPC_0 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_GPU_0 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_MSENC_0 */ + 0x00ff0024, /* MC_LATENCY_ALLOWANCE_HDA_0 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VIC_0 */ + 0x000000ff, /* MC_LATENCY_ALLOWANCE_VI2_0 */ + 0x000000ff, /* MC_LATENCY_ALLOWANCE_ISP2_0 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2_1 */ + 0x000000ff, /* MC_LATENCY_ALLOWANCE_ISP2B_0 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2B_1 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_0 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_1 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_2 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_3 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SATA_0 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_AFI_0 */ + }, + 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ + 0x73240000, /* EMC_CFG */ + 0x00000885, /* EMC_CFG_2 */ + 0x0004012c, /* EMC_SEL_DPD_CTRL */ + 0x002c0068, /* EMC_CFG_DIG_DLL */ + 0x80001221, /* Mode Register 0 */ + 0x80100003, /* Mode Register 1 */ + 0x80200008, /* Mode Register 2 */ + 0x00000000, /* Mode Register 4 */ + }, + { + 0x15, /* V5.0.1 */ + "04_68000_0_V5.0.1_V0.3", /* DVFS table version */ + 68000, /* SDRAM frequency */ + 800, /* min voltage */ + 800, /* gpu min voltage */ + "pllp_out0", /* clock source id */ + 0x4000000a, /* CLK_SOURCE_EMC */ + 167, /* number of burst_regs */ + 31, /* number of up_down_regs */ + { + 0x00000003, /* EMC_RC */ + 0x00000011, /* EMC_RFC */ + 0x00000000, /* EMC_RFC_SLR */ + 0x00000002, /* EMC_RAS */ + 0x00000000, /* EMC_RP */ + 0x00000004, /* EMC_R2W */ + 0x0000000a, /* EMC_W2R */ + 0x00000003, /* EMC_R2P */ + 0x0000000b, /* EMC_W2P */ + 0x00000000, /* EMC_RD_RCD */ + 0x00000000, /* EMC_WR_RCD */ + 0x00000003, /* EMC_RRD */ + 0x00000003, /* EMC_REXT */ + 0x00000000, /* EMC_WEXT */ + 0x00000006, /* EMC_WDV */ + 0x00000006, /* EMC_WDV_MASK */ + 0x00000006, /* EMC_QUSE */ + 0x00000002, /* EMC_QUSE_WIDTH */ + 0x00000000, /* EMC_IBDLY */ + 0x00000005, /* EMC_EINPUT */ + 0x00000005, /* EMC_EINPUT_DURATION */ + 0x00010000, /* EMC_PUTERM_EXTRA */ + 0x00000004, /* EMC_PUTERM_WIDTH */ + 0x00000000, /* EMC_PUTERM_ADJ */ + 0x00000000, /* EMC_CDB_CNTL_1 */ + 0x00000000, /* EMC_CDB_CNTL_2 */ + 0x00000000, /* EMC_CDB_CNTL_3 */ + 0x00000004, /* EMC_QRST */ + 0x0000000c, /* EMC_QSAFE */ + 0x0000000d, /* EMC_RDV */ + 0x0000000f, /* EMC_RDV_MASK */ + 0x00000202, /* EMC_REFRESH */ + 0x00000000, /* EMC_BURST_REFRESH_NUM */ + 0x00000080, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002, /* EMC_PDEX2WR */ + 0x00000002, /* EMC_PDEX2RD */ + 0x00000001, /* EMC_PCHG2PDEN */ + 0x00000000, /* EMC_ACT2PDEN */ + 0x0000000f, /* EMC_AR2PDEN */ + 0x0000000f, /* EMC_RW2PDEN */ + 0x00000013, /* EMC_TXSR */ + 0x00000013, /* EMC_TXSRDLL */ + 0x00000004, /* EMC_TCKE */ + 0x00000005, /* EMC_TCKESR */ + 0x00000004, /* EMC_TPD */ + 0x00000001, /* EMC_TFAW */ + 0x00000000, /* EMC_TRPAB */ + 0x00000005, /* EMC_TCLKSTABLE */ + 0x00000005, /* EMC_TCLKSTOP */ + 0x00000213, /* EMC_TREFBW */ + 0x00000000, /* EMC_FBIO_CFG6 */ + 0x00000000, /* EMC_ODT_WRITE */ + 0x00000000, /* EMC_ODT_READ */ + 0x1069aa98, /* EMC_FBIO_CFG5 */ + 0x002c00a0, /* EMC_CFG_DIG_DLL */ + 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000, /* EMC_DLL_XFORM_DQS0 */ + 0x00064000, /* EMC_DLL_XFORM_DQS1 */ + 0x00064000, /* EMC_DLL_XFORM_DQS2 */ + 0x00064000, /* EMC_DLL_XFORM_DQS3 */ + 0x00064000, /* EMC_DLL_XFORM_DQS4 */ + 0x00064000, /* EMC_DLL_XFORM_DQS5 */ + 0x00064000, /* EMC_DLL_XFORM_DQS6 */ + 0x00064000, /* EMC_DLL_XFORM_DQS7 */ + 0x00064000, /* EMC_DLL_XFORM_DQS8 */ + 0x00064000, /* EMC_DLL_XFORM_DQS9 */ + 0x00064000, /* EMC_DLL_XFORM_DQS10 */ + 0x00064000, /* EMC_DLL_XFORM_DQS11 */ + 0x00064000, /* EMC_DLL_XFORM_DQS12 */ + 0x00064000, /* EMC_DLL_XFORM_DQS13 */ + 0x00064000, /* EMC_DLL_XFORM_DQS14 */ + 0x00064000, /* EMC_DLL_XFORM_DQS15 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS15 */ + 0x0007c000, /* EMC_DLL_XFORM_DQ0 */ + 0x0007c000, /* EMC_DLL_XFORM_DQ1 */ + 0x0007c000, /* EMC_DLL_XFORM_DQ2 */ + 0x0007c000, /* EMC_DLL_XFORM_DQ3 */ + 0x00007c00, /* EMC_DLL_XFORM_DQ4 */ + 0x00007c00, /* EMC_DLL_XFORM_DQ5 */ + 0x00007c00, /* EMC_DLL_XFORM_DQ6 */ + 0x00007c00, /* EMC_DLL_XFORM_DQ7 */ + 0x100002a0, /* EMC_XM2CMDPADCTRL */ + 0x00000000, /* EMC_XM2CMDPADCTRL4 */ + 0x00111111, /* EMC_XM2CMDPADCTRL5 */ + 0x0030a11c, /* EMC_XM2DQSPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL3 */ + 0x77ffc085, /* EMC_XM2CLKPADCTRL */ + 0x00000e0e, /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108, /* EMC_XM2COMPPADCTRL */ + 0x07070004, /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee, /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400, /* EMC_XM2DQSPADCTRL3 */ + 0x00514514, /* EMC_XM2DQSPADCTRL4 */ + 0x00514514, /* EMC_XM2DQSPADCTRL5 */ + 0x51451400, /* EMC_XM2DQSPADCTRL6 */ + 0x0505003f, /* EMC_DSR_VTTGEN_DRV */ + 0x00000022, /* EMC_TXDSRVTTGEN */ + 0x00000000, /* EMC_FBIO_SPARE */ + 0x00000000, /* EMC_ZCAL_INTERVAL */ + 0x00000042, /* EMC_ZCAL_WAIT_CNT */ + 0x000e000e, /* EMC_MRS_WAIT_CNT */ + 0x000e000e, /* EMC_MRS_WAIT_CNT2 */ + 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ + 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ + 0xa1430000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_CTT */ + 0x00000004, /* EMC_CTT_DURATION */ + 0x0000f2f3, /* EMC_CFG_PIPE */ + 0x8000050e, /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a, /* EMC_QPOP */ + 0x00000001, /* MC_EMEM_ARB_CFG */ + 0x8000001e, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003, /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203, /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402, /* MC_EMEM_ARB_DA_COVERS */ + 0x74230403, /* MC_EMEM_ARB_MISC0 */ + 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ + }, + { + 0x00000001, /* MC_MLL_MPCORER_PTSA_RATE */ + 0x00000021, /* MC_PTSA_GRANT_DECREMENT */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_XUSB_0 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_XUSB_1 */ + 0x00ff00b0, /* MC_LATENCY_ALLOWANCE_TSEC_0 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMCA_0 */ + 0x00ff00ec, /* MC_LATENCY_ALLOWANCE_SDMMCAA_0 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMC_0 */ + 0x00ff00ec, /* MC_LATENCY_ALLOWANCE_SDMMCAB_0 */ + 0x00e90049, /* MC_LATENCY_ALLOWANCE_PPCS_0 */ + 0x00ff0080, /* MC_LATENCY_ALLOWANCE_PPCS_1 */ + 0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORE_0 */ + 0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORELP_0 */ + 0x000800ff, /* MC_LATENCY_ALLOWANCE_HC_0 */ + 0x000000ff, /* MC_LATENCY_ALLOWANCE_HC_1 */ + 0x00ff0004, /* MC_LATENCY_ALLOWANCE_AVPC_0 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_GPU_0 */ + 0x00ff00a3, /* MC_LATENCY_ALLOWANCE_MSENC_0 */ + 0x00ff0024, /* MC_LATENCY_ALLOWANCE_HDA_0 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VIC_0 */ + 0x000000ff, /* MC_LATENCY_ALLOWANCE_VI2_0 */ + 0x000000ef, /* MC_LATENCY_ALLOWANCE_ISP2_0 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2_1 */ + 0x000000ef, /* MC_LATENCY_ALLOWANCE_ISP2B_0 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2B_1 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_0 */ + 0x00ee00ef, /* MC_LATENCY_ALLOWANCE_VDE_1 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_2 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_3 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SATA_0 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_AFI_0 */ + }, + 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ + 0x73240000, /* EMC_CFG */ + 0x00000885, /* EMC_CFG_2 */ + 0x0004012c, /* EMC_SEL_DPD_CTRL */ + 0x002c0068, /* EMC_CFG_DIG_DLL */ + 0x80001221, /* Mode Register 0 */ + 0x80100003, /* Mode Register 1 */ + 0x80200008, /* Mode Register 2 */ + 0x00000000, /* Mode Register 4 */ + }, + { + 0x15, /* V5.0.1 */ + "04_102000_0_V5.0.1_V0.3", /* DVFS table version */ 102000, /* SDRAM frequency */ - 850, /* min voltage */ + 800, /* min voltage */ 800, /* gpu min voltage */ "pllp_out0", /* clock source id */ 0x40000006, /* CLK_SOURCE_EMC */ @@ -242,9 +691,9 @@ static struct tegra12_emc_table ardbeg_emc_table[] = { 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x03240000, /* EMC_CFG */ + 0x73240000, /* EMC_CFG */ 0x00000885, /* EMC_CFG_2 */ - 0x00040000, /* EMC_SEL_DPD_CTRL */ + 0x0004012c, /* EMC_SEL_DPD_CTRL */ 0x002c0068, /* EMC_CFG_DIG_DLL */ 0x80001221, /* Mode Register 0 */ 0x80100003, /* Mode Register 1 */ @@ -252,9 +701,10 @@ static struct tegra12_emc_table ardbeg_emc_table[] = { 0x00000000, /* Mode Register 4 */ }, { - 0x14, /* V5.0.1 */ + 0x15, /* V5.0.1 */ + "04_204000_0_V5.0.1_V0.3", /* DVFS table version */ 204000, /* SDRAM frequency */ - 850, /* min voltage */ + 800, /* min voltage */ 800, /* gpu min voltage */ "pllp_out0", /* clock source id */ 0x40000002, /* CLK_SOURCE_EMC */ @@ -465,9 +915,9 @@ static struct tegra12_emc_table ardbeg_emc_table[] = { 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x03200000, /* EMC_CFG */ + 0x73200000, /* EMC_CFG */ 0x0000088d, /* EMC_CFG_2 */ - 0x00040000, /* EMC_SEL_DPD_CTRL */ + 0x0004012c, /* EMC_SEL_DPD_CTRL */ 0x002c0068, /* EMC_CFG_DIG_DLL */ 0x80001221, /* Mode Register 0 */ 0x80100003, /* Mode Register 1 */ @@ -475,7 +925,680 @@ static struct tegra12_emc_table ardbeg_emc_table[] = { 0x00000000, /* Mode Register 4 */ }, { - 0x14, /* V5.0.1 */ + 0x15, /* V5.0.2 */ + "04_312000_2_V5.0.2_V0.3", /* DVFS table version */ + 312000, /* SDRAM frequency */ + 820, /* min voltage */ + 800, /* gpu min voltage */ + "pllm_out0", /* clock source id */ + 0x00000002, /* CLK_SOURCE_EMC */ + 167, /* number of burst_regs */ + 31, /* number of up_down_regs */ + { + 0x0000000d, /* EMC_RC */ + 0x00000050, /* EMC_RFC */ + 0x00000000, /* EMC_RFC_SLR */ + 0x00000009, /* EMC_RAS */ + 0x00000003, /* EMC_RP */ + 0x00000004, /* EMC_R2W */ + 0x00000008, /* EMC_W2R */ + 0x00000002, /* EMC_R2P */ + 0x00000009, /* EMC_W2P */ + 0x00000003, /* EMC_RD_RCD */ + 0x00000003, /* EMC_WR_RCD */ + 0x00000002, /* EMC_RRD */ + 0x00000002, /* EMC_REXT */ + 0x00000000, /* EMC_WEXT */ + 0x00000003, /* EMC_WDV */ + 0x00000003, /* EMC_WDV_MASK */ + 0x00000005, /* EMC_QUSE */ + 0x00000002, /* EMC_QUSE_WIDTH */ + 0x00000000, /* EMC_IBDLY */ + 0x00000002, /* EMC_EINPUT */ + 0x00000006, /* EMC_EINPUT_DURATION */ + 0x00030000, /* EMC_PUTERM_EXTRA */ + 0x00000004, /* EMC_PUTERM_WIDTH */ + 0x00000000, /* EMC_PUTERM_ADJ */ + 0x00000000, /* EMC_CDB_CNTL_1 */ + 0x00000000, /* EMC_CDB_CNTL_2 */ + 0x00000000, /* EMC_CDB_CNTL_3 */ + 0x00000002, /* EMC_QRST */ + 0x0000000d, /* EMC_QSAFE */ + 0x0000000e, /* EMC_RDV */ + 0x00000010, /* EMC_RDV_MASK */ + 0x00000942, /* EMC_REFRESH */ + 0x00000000, /* EMC_BURST_REFRESH_NUM */ + 0x00000250, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001, /* EMC_PDEX2WR */ + 0x00000008, /* EMC_PDEX2RD */ + 0x00000001, /* EMC_PCHG2PDEN */ + 0x00000000, /* EMC_ACT2PDEN */ + 0x0000004e, /* EMC_AR2PDEN */ + 0x0000000e, /* EMC_RW2PDEN */ + 0x00000055, /* EMC_TXSR */ + 0x00000200, /* EMC_TXSRDLL */ + 0x00000004, /* EMC_TCKE */ + 0x00000005, /* EMC_TCKESR */ + 0x00000004, /* EMC_TPD */ + 0x0000000a, /* EMC_TFAW */ + 0x00000000, /* EMC_TRPAB */ + 0x00000005, /* EMC_TCLKSTABLE */ + 0x00000005, /* EMC_TCLKSTOP */ + 0x00000982, /* EMC_TREFBW */ + 0x00000002, /* EMC_FBIO_CFG6 */ + 0x00000000, /* EMC_ODT_WRITE */ + 0x00000000, /* EMC_ODT_READ */ + 0x1049b898, /* EMC_FBIO_CFG5 */ + 0x002c00a0, /* EMC_CFG_DIG_DLL */ + 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00030000, /* EMC_DLL_XFORM_DQS0 */ + 0x00030000, /* EMC_DLL_XFORM_DQS1 */ + 0x00030000, /* EMC_DLL_XFORM_DQS2 */ + 0x00030000, /* EMC_DLL_XFORM_DQS3 */ + 0x00030000, /* EMC_DLL_XFORM_DQS4 */ + 0x00030000, /* EMC_DLL_XFORM_DQS5 */ + 0x00030000, /* EMC_DLL_XFORM_DQS6 */ + 0x00030000, /* EMC_DLL_XFORM_DQS7 */ + 0x00030000, /* EMC_DLL_XFORM_DQS8 */ + 0x00030000, /* EMC_DLL_XFORM_DQS9 */ + 0x00030000, /* EMC_DLL_XFORM_DQS10 */ + 0x00030000, /* EMC_DLL_XFORM_DQS11 */ + 0x00030000, /* EMC_DLL_XFORM_DQS12 */ + 0x00030000, /* EMC_DLL_XFORM_DQS13 */ + 0x00030000, /* EMC_DLL_XFORM_DQS14 */ + 0x00030000, /* EMC_DLL_XFORM_DQS15 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ + 0x00040000, /* EMC_DLL_XFORM_ADDR0 */ + 0x00040000, /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ + 0x00040000, /* EMC_DLL_XFORM_ADDR3 */ + 0x00040000, /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS15 */ + 0x00040000, /* EMC_DLL_XFORM_DQ0 */ + 0x00040000, /* EMC_DLL_XFORM_DQ1 */ + 0x00040000, /* EMC_DLL_XFORM_DQ2 */ + 0x00040000, /* EMC_DLL_XFORM_DQ3 */ + 0x00004000, /* EMC_DLL_XFORM_DQ4 */ + 0x00004000, /* EMC_DLL_XFORM_DQ5 */ + 0x00004000, /* EMC_DLL_XFORM_DQ6 */ + 0x00004000, /* EMC_DLL_XFORM_DQ7 */ + 0x10000280, /* EMC_XM2CMDPADCTRL */ + 0x00000000, /* EMC_XM2CMDPADCTRL4 */ + 0x00111111, /* EMC_XM2CMDPADCTRL5 */ + 0x01231339, /* EMC_XM2DQSPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081, /* EMC_XM2CLKPADCTRL */ + 0x00000505, /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108, /* EMC_XM2COMPPADCTRL */ + 0x07070004, /* EMC_XM2VTTGENPADCTRL */ + 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee, /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420, /* EMC_XM2DQSPADCTRL3 */ + 0x00514514, /* EMC_XM2DQSPADCTRL4 */ + 0x00514514, /* EMC_XM2DQSPADCTRL5 */ + 0x51451400, /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ + 0x0000009c, /* EMC_TXDSRVTTGEN */ + 0x00000000, /* EMC_FBIO_SPARE */ + 0x00020000, /* EMC_ZCAL_INTERVAL */ + 0x00000100, /* EMC_ZCAL_WAIT_CNT */ + 0x0170000e, /* EMC_MRS_WAIT_CNT */ + 0x0170000e, /* EMC_MRS_WAIT_CNT2 */ + 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ + 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ + 0xa1430000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_CTT */ + 0x00000004, /* EMC_CTT_DURATION */ + 0x0000d3b3, /* EMC_CFG_PIPE */ + 0x8000138d, /* EMC_DYN_SELF_REF_CONTROL */ + 0x00000009, /* EMC_QPOP */ + 0x0b000004, /* MC_EMEM_ARB_CFG */ + 0x80000040, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RP */ + 0x00000007, /* MC_EMEM_ARB_TIMING_RC */ + 0x00000004, /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000005, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040202, /* MC_EMEM_ARB_DA_TURNS */ + 0x000b0607, /* MC_EMEM_ARB_DA_COVERS */ + 0x76e50f08, /* MC_EMEM_ARB_MISC0 */ + 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ + }, + { + 0x00000005, /* MC_MLL_MPCORER_PTSA_RATE */ + 0x00000096, /* MC_PTSA_GRANT_DECREMENT */ + 0x00ff0047, /* MC_LATENCY_ALLOWANCE_XUSB_0 */ + 0x00ff0047, /* MC_LATENCY_ALLOWANCE_XUSB_1 */ + 0x00ff003c, /* MC_LATENCY_ALLOWANCE_TSEC_0 */ + 0x00ff0090, /* MC_LATENCY_ALLOWANCE_SDMMCA_0 */ + 0x00ff0041, /* MC_LATENCY_ALLOWANCE_SDMMCAA_0 */ + 0x00ff0090, /* MC_LATENCY_ALLOWANCE_SDMMC_0 */ + 0x00ff0041, /* MC_LATENCY_ALLOWANCE_SDMMCAB_0 */ + 0x00330049, /* MC_LATENCY_ALLOWANCE_PPCS_0 */ + 0x00ff0080, /* MC_LATENCY_ALLOWANCE_PPCS_1 */ + 0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORE_0 */ + 0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORELP_0 */ + 0x00080039, /* MC_LATENCY_ALLOWANCE_HC_0 */ + 0x000000ff, /* MC_LATENCY_ALLOWANCE_HC_1 */ + 0x00ff0004, /* MC_LATENCY_ALLOWANCE_AVPC_0 */ + 0x00ff0041, /* MC_LATENCY_ALLOWANCE_GPU_0 */ + 0x00ff002c, /* MC_LATENCY_ALLOWANCE_MSENC_0 */ + 0x00ff0024, /* MC_LATENCY_ALLOWANCE_HDA_0 */ + 0x00ff0046, /* MC_LATENCY_ALLOWANCE_VIC_0 */ + 0x000000ff, /* MC_LATENCY_ALLOWANCE_VI2_0 */ + 0x00000036, /* MC_LATENCY_ALLOWANCE_ISP2_0 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2_1 */ + 0x00000036, /* MC_LATENCY_ALLOWANCE_ISP2B_0 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2B_1 */ + 0x00d400ff, /* MC_LATENCY_ALLOWANCE_VDE_0 */ + 0x00510034, /* MC_LATENCY_ALLOWANCE_VDE_1 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_2 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_3 */ + 0x00ff0082, /* MC_LATENCY_ALLOWANCE_SATA_0 */ + 0x00ff0047, /* MC_LATENCY_ALLOWANCE_AFI_0 */ + }, + 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ + 0x73340000, /* EMC_CFG */ + 0x0000088d, /* EMC_CFG_2 */ + 0x0004012c, /* EMC_SEL_DPD_CTRL */ + 0x002c0068, /* EMC_CFG_DIG_DLL */ + 0x80000321, /* Mode Register 0 */ + 0x80100002, /* Mode Register 1 */ + 0x80200000, /* Mode Register 2 */ + 0x00000000, /* Mode Register 4 */ + }, + { + 0x15, /* V5.0.2 */ + "04_396000_1_V5.0.2_V0.3", /* DVFS table version */ + 396000, /* SDRAM frequency */ + 870, /* min voltage */ + 800, /* gpu min voltage */ + "pllc_out0", /* clock source id */ + 0x20000002, /* CLK_SOURCE_EMC */ + 167, /* number of burst_regs */ + 31, /* number of up_down_regs */ + { + 0x00000011, /* EMC_RC */ + 0x00000066, /* EMC_RFC */ + 0x00000000, /* EMC_RFC_SLR */ + 0x0000000c, /* EMC_RAS */ + 0x00000004, /* EMC_RP */ + 0x00000004, /* EMC_R2W */ + 0x00000008, /* EMC_W2R */ + 0x00000002, /* EMC_R2P */ + 0x0000000a, /* EMC_W2P */ + 0x00000004, /* EMC_RD_RCD */ + 0x00000004, /* EMC_WR_RCD */ + 0x00000002, /* EMC_RRD */ + 0x00000002, /* EMC_REXT */ + 0x00000000, /* EMC_WEXT */ + 0x00000003, /* EMC_WDV */ + 0x00000003, /* EMC_WDV_MASK */ + 0x00000005, /* EMC_QUSE */ + 0x00000002, /* EMC_QUSE_WIDTH */ + 0x00000000, /* EMC_IBDLY */ + 0x00000002, /* EMC_EINPUT */ + 0x00000006, /* EMC_EINPUT_DURATION */ + 0x00030000, /* EMC_PUTERM_EXTRA */ + 0x00000004, /* EMC_PUTERM_WIDTH */ + 0x00000000, /* EMC_PUTERM_ADJ */ + 0x00000000, /* EMC_CDB_CNTL_1 */ + 0x00000000, /* EMC_CDB_CNTL_2 */ + 0x00000000, /* EMC_CDB_CNTL_3 */ + 0x00000002, /* EMC_QRST */ + 0x0000000d, /* EMC_QSAFE */ + 0x0000000e, /* EMC_RDV */ + 0x00000010, /* EMC_RDV_MASK */ + 0x00000bd1, /* EMC_REFRESH */ + 0x00000000, /* EMC_BURST_REFRESH_NUM */ + 0x000002f4, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001, /* EMC_PDEX2WR */ + 0x00000008, /* EMC_PDEX2RD */ + 0x00000001, /* EMC_PCHG2PDEN */ + 0x00000000, /* EMC_ACT2PDEN */ + 0x00000063, /* EMC_AR2PDEN */ + 0x0000000f, /* EMC_RW2PDEN */ + 0x0000006c, /* EMC_TXSR */ + 0x00000200, /* EMC_TXSRDLL */ + 0x00000004, /* EMC_TCKE */ + 0x00000005, /* EMC_TCKESR */ + 0x00000004, /* EMC_TPD */ + 0x0000000d, /* EMC_TFAW */ + 0x00000000, /* EMC_TRPAB */ + 0x00000005, /* EMC_TCLKSTABLE */ + 0x00000005, /* EMC_TCLKSTOP */ + 0x00000c11, /* EMC_TREFBW */ + 0x00000002, /* EMC_FBIO_CFG6 */ + 0x00000000, /* EMC_ODT_WRITE */ + 0x00000000, /* EMC_ODT_READ */ + 0x1049b898, /* EMC_FBIO_CFG5 */ + 0x002c00a0, /* EMC_CFG_DIG_DLL */ + 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00030000, /* EMC_DLL_XFORM_DQS0 */ + 0x00030000, /* EMC_DLL_XFORM_DQS1 */ + 0x00030000, /* EMC_DLL_XFORM_DQS2 */ + 0x00030000, /* EMC_DLL_XFORM_DQS3 */ + 0x00030000, /* EMC_DLL_XFORM_DQS4 */ + 0x00030000, /* EMC_DLL_XFORM_DQS5 */ + 0x00030000, /* EMC_DLL_XFORM_DQS6 */ + 0x00030000, /* EMC_DLL_XFORM_DQS7 */ + 0x00030000, /* EMC_DLL_XFORM_DQS8 */ + 0x00030000, /* EMC_DLL_XFORM_DQS9 */ + 0x00030000, /* EMC_DLL_XFORM_DQS10 */ + 0x00030000, /* EMC_DLL_XFORM_DQS11 */ + 0x00030000, /* EMC_DLL_XFORM_DQS12 */ + 0x00030000, /* EMC_DLL_XFORM_DQS13 */ + 0x00030000, /* EMC_DLL_XFORM_DQS14 */ + 0x00030000, /* EMC_DLL_XFORM_DQS15 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ + 0x00070000, /* EMC_DLL_XFORM_ADDR0 */ + 0x00070000, /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ + 0x00070000, /* EMC_DLL_XFORM_ADDR3 */ + 0x00070000, /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS15 */ + 0x00044000, /* EMC_DLL_XFORM_DQ0 */ + 0x00044000, /* EMC_DLL_XFORM_DQ1 */ + 0x00044000, /* EMC_DLL_XFORM_DQ2 */ + 0x00044000, /* EMC_DLL_XFORM_DQ3 */ + 0x00004400, /* EMC_DLL_XFORM_DQ4 */ + 0x00004400, /* EMC_DLL_XFORM_DQ5 */ + 0x00004400, /* EMC_DLL_XFORM_DQ6 */ + 0x00004400, /* EMC_DLL_XFORM_DQ7 */ + 0x100002a0, /* EMC_XM2CMDPADCTRL */ + 0x00000000, /* EMC_XM2CMDPADCTRL4 */ + 0x00111111, /* EMC_XM2CMDPADCTRL5 */ + 0x0123133d, /* EMC_XM2DQSPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL3 */ + 0x77ffc085, /* EMC_XM2CLKPADCTRL */ + 0x00000505, /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108, /* EMC_XM2COMPPADCTRL */ + 0x07070004, /* EMC_XM2VTTGENPADCTRL */ + 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee, /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420, /* EMC_XM2DQSPADCTRL3 */ + 0x00514514, /* EMC_XM2DQSPADCTRL4 */ + 0x00514514, /* EMC_XM2DQSPADCTRL5 */ + 0x51451400, /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ + 0x000000c6, /* EMC_TXDSRVTTGEN */ + 0x00000000, /* EMC_FBIO_SPARE */ + 0x00020000, /* EMC_ZCAL_INTERVAL */ + 0x00000100, /* EMC_ZCAL_WAIT_CNT */ + 0x015b000e, /* EMC_MRS_WAIT_CNT */ + 0x015b000e, /* EMC_MRS_WAIT_CNT2 */ + 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ + 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ + 0xa1430000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_CTT */ + 0x00000004, /* EMC_CTT_DURATION */ + 0x0000d3b3, /* EMC_CFG_PIPE */ + 0x8000188b, /* EMC_DYN_SELF_REF_CONTROL */ + 0x00000009, /* EMC_QPOP */ + 0x0f000005, /* MC_EMEM_ARB_CFG */ + 0x80000040, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RP */ + 0x00000009, /* MC_EMEM_ARB_TIMING_RC */ + 0x00000005, /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000007, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040202, /* MC_EMEM_ARB_DA_TURNS */ + 0x000d0709, /* MC_EMEM_ARB_DA_COVERS */ + 0x7586120a, /* MC_EMEM_ARB_MISC0 */ + 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ + }, + { + 0x0000000a, /* MC_MLL_MPCORER_PTSA_RATE */ + 0x000000be, /* MC_PTSA_GRANT_DECREMENT */ + 0x00ff0038, /* MC_LATENCY_ALLOWANCE_XUSB_0 */ + 0x00ff0038, /* MC_LATENCY_ALLOWANCE_XUSB_1 */ + 0x00ff003c, /* MC_LATENCY_ALLOWANCE_TSEC_0 */ + 0x00ff0090, /* MC_LATENCY_ALLOWANCE_SDMMCA_0 */ + 0x00ff0041, /* MC_LATENCY_ALLOWANCE_SDMMCAA_0 */ + 0x00ff0090, /* MC_LATENCY_ALLOWANCE_SDMMC_0 */ + 0x00ff0041, /* MC_LATENCY_ALLOWANCE_SDMMCAB_0 */ + 0x00280049, /* MC_LATENCY_ALLOWANCE_PPCS_0 */ + 0x00ff0080, /* MC_LATENCY_ALLOWANCE_PPCS_1 */ + 0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORE_0 */ + 0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORELP_0 */ + 0x0008002d, /* MC_LATENCY_ALLOWANCE_HC_0 */ + 0x000000ff, /* MC_LATENCY_ALLOWANCE_HC_1 */ + 0x00ff0004, /* MC_LATENCY_ALLOWANCE_AVPC_0 */ + 0x00ff0033, /* MC_LATENCY_ALLOWANCE_GPU_0 */ + 0x00ff0022, /* MC_LATENCY_ALLOWANCE_MSENC_0 */ + 0x00ff0024, /* MC_LATENCY_ALLOWANCE_HDA_0 */ + 0x00ff0037, /* MC_LATENCY_ALLOWANCE_VIC_0 */ + 0x000000ff, /* MC_LATENCY_ALLOWANCE_VI2_0 */ + 0x00000036, /* MC_LATENCY_ALLOWANCE_ISP2_0 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2_1 */ + 0x00000036, /* MC_LATENCY_ALLOWANCE_ISP2B_0 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2B_1 */ + 0x00d400ff, /* MC_LATENCY_ALLOWANCE_VDE_0 */ + 0x00510029, /* MC_LATENCY_ALLOWANCE_VDE_1 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_2 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_3 */ + 0x00ff0066, /* MC_LATENCY_ALLOWANCE_SATA_0 */ + 0x00ff0038, /* MC_LATENCY_ALLOWANCE_AFI_0 */ + }, + 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ + 0x73340000, /* EMC_CFG */ + 0x0000088d, /* EMC_CFG_2 */ + 0x0004012c, /* EMC_SEL_DPD_CTRL */ + 0x002c0068, /* EMC_CFG_DIG_DLL */ + 0x80000521, /* Mode Register 0 */ + 0x80100002, /* Mode Register 1 */ + 0x80200000, /* Mode Register 2 */ + 0x00000000, /* Mode Register 4 */ + }, + { + 0x15, /* NoRegCalcVersion */ + "04_624000_2_NoRegCalcVersion_V0.3", /* DVFS table version */ + 624000, /* SDRAM frequency */ + 910, /* min voltage */ + 900, /* gpu min voltage */ + "pllm_ud", /* clock source id */ + 0x80000000, /* CLK_SOURCE_EMC */ + 167, /* number of burst_regs */ + 31, /* number of up_down_regs */ + { + 0x0000001c, /* EMC_RC */ + 0x000000a1, /* EMC_RFC */ + 0x00000000, /* EMC_RFC_SLR */ + 0x00000014, /* EMC_RAS */ + 0x00000007, /* EMC_RP */ + 0x00000007, /* EMC_R2W */ + 0x0000000b, /* EMC_W2R */ + 0x00000003, /* EMC_R2P */ + 0x00000010, /* EMC_W2P */ + 0x00000007, /* EMC_RD_RCD */ + 0x00000007, /* EMC_WR_RCD */ + 0x00000002, /* EMC_RRD */ + 0x00000002, /* EMC_REXT */ + 0x00000000, /* EMC_WEXT */ + 0x00000005, /* EMC_WDV */ + 0x00000005, /* EMC_WDV_MASK */ + 0x0000000a, /* EMC_QUSE */ + 0x00000002, /* EMC_QUSE_WIDTH */ + 0x00000000, /* EMC_IBDLY */ + 0x00000003, /* EMC_EINPUT */ + 0x0000000b, /* EMC_EINPUT_DURATION */ + 0x00080000, /* EMC_PUTERM_EXTRA */ + 0x00000004, /* EMC_PUTERM_WIDTH */ + 0x00000000, /* EMC_PUTERM_ADJ */ + 0x00000000, /* EMC_CDB_CNTL_1 */ + 0x00000000, /* EMC_CDB_CNTL_2 */ + 0x00000000, /* EMC_CDB_CNTL_3 */ + 0x00000002, /* EMC_QRST */ + 0x00000012, /* EMC_QSAFE */ + 0x00000016, /* EMC_RDV */ + 0x00000018, /* EMC_RDV_MASK */ + 0x000012c3, /* EMC_REFRESH */ + 0x00000000, /* EMC_BURST_REFRESH_NUM */ + 0x000004b0, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002, /* EMC_PDEX2WR */ + 0x0000000d, /* EMC_PDEX2RD */ + 0x00000001, /* EMC_PCHG2PDEN */ + 0x00000000, /* EMC_ACT2PDEN */ + 0x0000009c, /* EMC_AR2PDEN */ + 0x00000015, /* EMC_RW2PDEN */ + 0x000000a9, /* EMC_TXSR */ + 0x00000200, /* EMC_TXSRDLL */ + 0x00000004, /* EMC_TCKE */ + 0x00000005, /* EMC_TCKESR */ + 0x00000004, /* EMC_TPD */ + 0x00000016, /* EMC_TFAW */ + 0x00000000, /* EMC_TRPAB */ + 0x00000007, /* EMC_TCLKSTABLE */ + 0x00000007, /* EMC_TCLKSTOP */ + 0x00001304, /* EMC_TREFBW */ + 0x00000002, /* EMC_FBIO_CFG6 */ + 0x00000000, /* EMC_ODT_WRITE */ + 0x00000000, /* EMC_ODT_READ */ + 0x1049b898, /* EMC_FBIO_CFG5 */ + 0xe00d01b1, /* EMC_CFG_DIG_DLL */ + 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00000008, /* EMC_DLL_XFORM_DQS0 */ + 0x00000008, /* EMC_DLL_XFORM_DQS1 */ + 0x00000008, /* EMC_DLL_XFORM_DQS2 */ + 0x00000008, /* EMC_DLL_XFORM_DQS3 */ + 0x00000008, /* EMC_DLL_XFORM_DQS4 */ + 0x00000008, /* EMC_DLL_XFORM_DQS5 */ + 0x00000008, /* EMC_DLL_XFORM_DQS6 */ + 0x00000008, /* EMC_DLL_XFORM_DQS7 */ + 0x00000008, /* EMC_DLL_XFORM_DQS8 */ + 0x00000008, /* EMC_DLL_XFORM_DQS9 */ + 0x00000008, /* EMC_DLL_XFORM_DQS10 */ + 0x00000008, /* EMC_DLL_XFORM_DQS11 */ + 0x00000008, /* EMC_DLL_XFORM_DQS12 */ + 0x00000008, /* EMC_DLL_XFORM_DQS13 */ + 0x00000008, /* EMC_DLL_XFORM_DQS14 */ + 0x00000008, /* EMC_DLL_XFORM_DQS15 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ + 0x0000400e, /* EMC_DLL_XFORM_ADDR0 */ + 0x0000400e, /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ + 0x0000400e, /* EMC_DLL_XFORM_ADDR3 */ + 0x0000400e, /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS15 */ + 0x0000000a, /* EMC_DLL_XFORM_DQ0 */ + 0x0000000a, /* EMC_DLL_XFORM_DQ1 */ + 0x0000000a, /* EMC_DLL_XFORM_DQ2 */ + 0x0000000a, /* EMC_DLL_XFORM_DQ3 */ + 0x0000000a, /* EMC_DLL_XFORM_DQ4 */ + 0x0000000a, /* EMC_DLL_XFORM_DQ5 */ + 0x0000000a, /* EMC_DLL_XFORM_DQ6 */ + 0x0000000a, /* EMC_DLL_XFORM_DQ7 */ + 0x100002a0, /* EMC_XM2CMDPADCTRL */ + 0x00000000, /* EMC_XM2CMDPADCTRL4 */ + 0x00111111, /* EMC_XM2CMDPADCTRL5 */ + 0x0020013d, /* EMC_XM2DQSPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL3 */ + 0x77ffc085, /* EMC_XM2CLKPADCTRL */ + 0x00000505, /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108, /* EMC_XM2COMPPADCTRL */ + 0x07070004, /* EMC_XM2VTTGENPADCTRL */ + 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee, /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420, /* EMC_XM2DQSPADCTRL3 */ + 0x00514514, /* EMC_XM2DQSPADCTRL4 */ + 0x00514514, /* EMC_XM2DQSPADCTRL5 */ + 0x51451400, /* EMC_XM2DQSPADCTRL6 */ + 0x0505003f, /* EMC_DSR_VTTGEN_DRV */ + 0x00000000, /* EMC_TXDSRVTTGEN */ + 0x00000000, /* EMC_FBIO_SPARE */ + 0x00020000, /* EMC_ZCAL_INTERVAL */ + 0x00000100, /* EMC_ZCAL_WAIT_CNT */ + 0x0122000e, /* EMC_MRS_WAIT_CNT */ + 0x0122000e, /* EMC_MRS_WAIT_CNT2 */ + 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ + 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ + 0xa1430000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_CTT */ + 0x00000004, /* EMC_CTT_DURATION */ + 0x000040a0, /* EMC_CFG_PIPE */ + 0x80002617, /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000e, /* EMC_QPOP */ + 0x06000009, /* MC_EMEM_ARB_CFG */ + 0x80000040, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000003, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000004, /* MC_EMEM_ARB_TIMING_RP */ + 0x0000000f, /* MC_EMEM_ARB_TIMING_RC */ + 0x00000009, /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000b, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000b, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000005, /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000007, /* MC_EMEM_ARB_TIMING_W2R */ + 0x07050202, /* MC_EMEM_ARB_DA_TURNS */ + 0x00130b0f, /* MC_EMEM_ARB_DA_COVERS */ + 0x736a1d10, /* MC_EMEM_ARB_MISC0 */ + 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ + }, + { + 0x0000000f, /* MC_MLL_MPCORER_PTSA_RATE */ + 0x0000012b, /* MC_PTSA_GRANT_DECREMENT */ + 0x00a40038, /* MC_LATENCY_ALLOWANCE_XUSB_0 */ + 0x00a40038, /* MC_LATENCY_ALLOWANCE_XUSB_1 */ + 0x00a4003c, /* MC_LATENCY_ALLOWANCE_TSEC_0 */ + 0x00a40090, /* MC_LATENCY_ALLOWANCE_SDMMCA_0 */ + 0x00a40041, /* MC_LATENCY_ALLOWANCE_SDMMCAA_0 */ + 0x00a40090, /* MC_LATENCY_ALLOWANCE_SDMMC_0 */ + 0x00a40041, /* MC_LATENCY_ALLOWANCE_SDMMCAB_0 */ + 0x00270049, /* MC_LATENCY_ALLOWANCE_PPCS_0 */ + 0x00a40080, /* MC_LATENCY_ALLOWANCE_PPCS_1 */ + 0x00a40004, /* MC_LATENCY_ALLOWANCE_MPCORE_0 */ + 0x00a40004, /* MC_LATENCY_ALLOWANCE_MPCORELP_0 */ + 0x0008001c, /* MC_LATENCY_ALLOWANCE_HC_0 */ + 0x000000a4, /* MC_LATENCY_ALLOWANCE_HC_1 */ + 0x00a40004, /* MC_LATENCY_ALLOWANCE_AVPC_0 */ + 0x00a40020, /* MC_LATENCY_ALLOWANCE_GPU_0 */ + 0x00a40018, /* MC_LATENCY_ALLOWANCE_MSENC_0 */ + 0x00a40024, /* MC_LATENCY_ALLOWANCE_HDA_0 */ + 0x00a40023, /* MC_LATENCY_ALLOWANCE_VIC_0 */ + 0x000000a4, /* MC_LATENCY_ALLOWANCE_VI2_0 */ + 0x00000036, /* MC_LATENCY_ALLOWANCE_ISP2_0 */ + 0x00a400a4, /* MC_LATENCY_ALLOWANCE_ISP2_1 */ + 0x00000036, /* MC_LATENCY_ALLOWANCE_ISP2B_0 */ + 0x00a400a4, /* MC_LATENCY_ALLOWANCE_ISP2B_1 */ + 0x00d400ff, /* MC_LATENCY_ALLOWANCE_VDE_0 */ + 0x00510029, /* MC_LATENCY_ALLOWANCE_VDE_1 */ + 0x00a400a4, /* MC_LATENCY_ALLOWANCE_VDE_2 */ + 0x00a400a4, /* MC_LATENCY_ALLOWANCE_VDE_3 */ + 0x00a40065, /* MC_LATENCY_ALLOWANCE_SATA_0 */ + 0x00a40024, /* MC_LATENCY_ALLOWANCE_AFI_0 */ + }, + 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ + 0x73300000, /* EMC_CFG */ + 0x0000089d, /* EMC_CFG_2 */ + 0x00040128, /* EMC_SEL_DPD_CTRL */ + 0xe00d0169, /* EMC_CFG_DIG_DLL */ + 0x80000b61, /* Mode Register 0 */ + 0x80100002, /* Mode Register 1 */ + 0x80200010, /* Mode Register 2 */ + 0x00000000, /* Mode Register 4 */ + }, + { + 0x15, /* V5.0.1 */ + "04_792000_2_V5.0.1_V0.3", /* DVFS table version */ 792000, /* SDRAM frequency */ 1000, /* min voltage */ 1100, /* gpu min voltage */ @@ -688,7 +1811,7 @@ static struct tegra12_emc_table ardbeg_emc_table[] = { 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x03300000, /* EMC_CFG */ + 0x73300000, /* EMC_CFG */ 0x0000089d, /* EMC_CFG_2 */ 0x00040000, /* EMC_SEL_DPD_CTRL */ 0xe0070169, /* EMC_CFG_DIG_DLL */ @@ -698,7 +1821,8 @@ static struct tegra12_emc_table ardbeg_emc_table[] = { 0x00000000, /* Mode Register 4 */ }, { - 0x14, /* V5.0.1 */ + 0x15, /* V5.0.4 */ + "04_924000_4_V5.0.4_V0.3", /* DVFS table version */ 924000, /* SDRAM frequency */ 1100, /* min voltage */ 1100, /* gpu min voltage */ @@ -708,7 +1832,7 @@ static struct tegra12_emc_table ardbeg_emc_table[] = { 31, /* number of up_down_regs */ { 0x0000002b, /* EMC_RC */ - 0x000000ef, /* EMC_RFC */ + 0x000000f0, /* EMC_RFC */ 0x00000000, /* EMC_RFC_SLR */ 0x0000001e, /* EMC_RAS */ 0x0000000b, /* EMC_RP */ @@ -721,33 +1845,33 @@ static struct tegra12_emc_table ardbeg_emc_table[] = { 0x00000004, /* EMC_RRD */ 0x00000002, /* EMC_REXT */ 0x00000000, /* EMC_WEXT */ - 0x00000006, /* EMC_WDV */ - 0x00000006, /* EMC_WDV_MASK */ - 0x0000000d, /* EMC_QUSE */ + 0x00000007, /* EMC_WDV */ + 0x00000007, /* EMC_WDV_MASK */ + 0x0000000e, /* EMC_QUSE */ 0x00000002, /* EMC_QUSE_WIDTH */ 0x00000000, /* EMC_IBDLY */ - 0x00000002, /* EMC_EINPUT */ + 0x00000003, /* EMC_EINPUT */ 0x0000000e, /* EMC_EINPUT_DURATION */ - 0x000a0000, /* EMC_PUTERM_EXTRA */ + 0x000b0000, /* EMC_PUTERM_EXTRA */ 0x00000004, /* EMC_PUTERM_WIDTH */ 0x00000000, /* EMC_PUTERM_ADJ */ 0x00000000, /* EMC_CDB_CNTL_1 */ 0x00000000, /* EMC_CDB_CNTL_2 */ 0x00000000, /* EMC_CDB_CNTL_3 */ - 0x00000001, /* EMC_QRST */ + 0x00000002, /* EMC_QRST */ 0x00000015, /* EMC_QSAFE */ - 0x0000001c, /* EMC_RDV */ - 0x0000001e, /* EMC_RDV_MASK */ - 0x00001be9, /* EMC_REFRESH */ + 0x0000001a, /* EMC_RDV */ + 0x0000001c, /* EMC_RDV_MASK */ + 0x00001be7, /* EMC_REFRESH */ 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x000006fa, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x000006f9, /* EMC_PRE_REFRESH_REQ_CNT */ 0x00000004, /* EMC_PDEX2WR */ 0x00000015, /* EMC_PDEX2RD */ 0x00000001, /* EMC_PCHG2PDEN */ 0x00000000, /* EMC_ACT2PDEN */ - 0x000000e6, /* EMC_AR2PDEN */ + 0x000000e7, /* EMC_AR2PDEN */ 0x0000001b, /* EMC_RW2PDEN */ - 0x000000fa, /* EMC_TXSR */ + 0x00000132, /* EMC_TXSR */ 0x00000200, /* EMC_TXSRDLL */ 0x00000006, /* EMC_TCKE */ 0x00000007, /* EMC_TCKESR */ @@ -756,7 +1880,7 @@ static struct tegra12_emc_table ardbeg_emc_table[] = { 0x00000000, /* EMC_TRPAB */ 0x0000000a, /* EMC_TCLKSTABLE */ 0x0000000a, /* EMC_TCLKSTOP */ - 0x00001c29, /* EMC_TREFBW */ + 0x00001c28, /* EMC_TREFBW */ 0x00000000, /* EMC_FBIO_CFG6 */ 0x00000000, /* EMC_ODT_WRITE */ 0x00000000, /* EMC_ODT_READ */ @@ -787,11 +1911,11 @@ static struct tegra12_emc_table ardbeg_emc_table[] = { 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x0000400e, /* EMC_DLL_XFORM_ADDR0 */ - 0x0000400e, /* EMC_DLL_XFORM_ADDR1 */ + 0x00040000, /* EMC_DLL_XFORM_ADDR0 */ + 0x00040000, /* EMC_DLL_XFORM_ADDR1 */ 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0000400e, /* EMC_DLL_XFORM_ADDR3 */ - 0x0000400e, /* EMC_DLL_XFORM_ADDR4 */ + 0x00040000, /* EMC_DLL_XFORM_ADDR3 */ + 0x00040000, /* EMC_DLL_XFORM_ADDR4 */ 0x00000000, /* EMC_DLL_XFORM_ADDR5 */ 0x00000000, /* EMC_DLL_XFORM_QUSE8 */ 0x00000000, /* EMC_DLL_XFORM_QUSE9 */ @@ -828,7 +1952,7 @@ static struct tegra12_emc_table ardbeg_emc_table[] = { 0x100002a0, /* EMC_XM2CMDPADCTRL */ 0x00000000, /* EMC_XM2CMDPADCTRL4 */ 0x00111111, /* EMC_XM2CMDPADCTRL5 */ - 0x0020013d, /* EMC_XM2DQSPADCTRL2 */ + 0x0120113d, /* EMC_XM2DQSPADCTRL2 */ 0x00000000, /* EMC_XM2DQPADCTRL2 */ 0x00000000, /* EMC_XM2DQPADCTRL3 */ 0x77ffc085, /* EMC_XM2CLKPADCTRL */ @@ -846,15 +1970,15 @@ static struct tegra12_emc_table ardbeg_emc_table[] = { 0x00000000, /* EMC_FBIO_SPARE */ 0x00020000, /* EMC_ZCAL_INTERVAL */ 0x00000128, /* EMC_ZCAL_WAIT_CNT */ - 0x00ce000e, /* EMC_MRS_WAIT_CNT */ - 0x00ce000e, /* EMC_MRS_WAIT_CNT2 */ + 0x00cd000e, /* EMC_MRS_WAIT_CNT */ + 0x00cd000e, /* EMC_MRS_WAIT_CNT2 */ 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ 0xa1430000, /* EMC_AUTO_CAL_CONFIG */ 0x00000000, /* EMC_CTT */ 0x00000004, /* EMC_CTT_DURATION */ - 0x00000000, /* EMC_CFG_PIPE */ - 0x800037ed, /* EMC_DYN_SELF_REF_CONTROL */ + 0x00004080, /* EMC_CFG_PIPE */ + 0x800037ea, /* EMC_DYN_SELF_REF_CONTROL */ 0x00000011, /* EMC_QPOP */ 0x0e00000d, /* MC_EMEM_ARB_CFG */ 0x80000040, /* MC_EMEM_ARB_OUTSTANDING_REQ */ @@ -872,7 +1996,7 @@ static struct tegra12_emc_table ardbeg_emc_table[] = { 0x00000009, /* MC_EMEM_ARB_TIMING_W2R */ 0x09060202, /* MC_EMEM_ARB_DA_TURNS */ 0x001a1016, /* MC_EMEM_ARB_DA_COVERS */ - 0x734e2a17, /* MC_EMEM_ARB_MISC0 */ + 0x738e2a17, /* MC_EMEM_ARB_MISC0 */ 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ }, { @@ -911,8 +2035,8 @@ static struct tegra12_emc_table ardbeg_emc_table[] = { 0x0000004c, /* EMC_ZCAL_WAIT_CNT after clock change */ 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x03300000, /* EMC_CFG */ - 0x000008a5, /* EMC_CFG_2 */ + 0x73300000, /* EMC_CFG */ + 0x0000089d, /* EMC_CFG_2 */ 0x00040000, /* EMC_SEL_DPD_CTRL */ 0xe0040169, /* EMC_CFG_DIG_DLL */ 0x80000f15, /* Mode Register 0 */ @@ -925,6 +2049,7 @@ static struct tegra12_emc_table ardbeg_emc_table[] = { + static struct tegra12_emc_pdata ardbeg_emc_pdata = { .description = "ardbeg_emc_tables", .tables = ardbeg_emc_table, @@ -943,7 +2068,6 @@ int __init ardbeg_emc_init(void) switch (bi.board_id) { case BOARD_E1780: - case BOARD_E1781: pr_info("Loading Ardbeg EMC tables.\n"); tegra_emc_device.dev.platform_data = &ardbeg_emc_pdata; break; |