arm: tegra: thermal: new ATE rev and margins

Added check for new ATE rev (0.9+).
Added WAR for ATE revs 0.9-0.11 - continue to use PLL-TSOSC for thermals.

Updated thermal thresholds and CPU and GPU EDP margins per thermal
margins spreadsheet.

Bug 1429685
Bug 1510809
Bug 1511626

Change-Id: I78528be0ed6b01625dd464054fbbf39c810c8873
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/407793
Reviewed-by: Automatic_Commit_Validation_User

1 files changed, 96 insertions, 16 deletions

diff --git a/arch/arm/mach-tegra/board-ardbeg-power.c b/arch/arm/mach-tegra/board-ardbeg-power.c
index e692bf5375ae..faf492ec9722 100644
--- a/arch/arm/mach-tegra/board-ardbeg-power.c
+++ b/arch/arm/mach-tegra/board-ardbeg-power.c
@@ -640,7 +640,7 @@ static struct soctherm_platform_data t132ref_v1_soctherm_data = {
 		[THERM_CPU] = {
 			.zone_enable = true,
 			.passive_delay = 1000,
-			.hotspot_offset = 6000,
+			.hotspot_offset = 10000,
 		},
 		[THERM_PLL] = {
 			.zone_enable = true,
@@ -649,21 +649,87 @@ static struct soctherm_platform_data t132ref_v1_soctherm_data = {
 			.trips = {
 				{
 					.cdev_type = "tegra-shutdown",
-					.trip_temp = 99000,
+					.trip_temp = 97000,
 					.trip_type = THERMAL_TRIP_CRITICAL,
 					.upper = THERMAL_NO_LIMIT,
 					.lower = THERMAL_NO_LIMIT,
 				},
 				{
 					.cdev_type = "tegra-heavy",
-					.trip_temp = 96000,
+					.trip_temp = 94000,
 					.trip_type = THERMAL_TRIP_HOT,
 					.upper = THERMAL_NO_LIMIT,
 					.lower = THERMAL_NO_LIMIT,
 				},
 				{
 					.cdev_type = "cpu-balanced",
-					.trip_temp = 86000,
+					.trip_temp = 84000,
+					.trip_type = THERMAL_TRIP_PASSIVE,
+					.upper = THERMAL_NO_LIMIT,
+					.lower = THERMAL_NO_LIMIT,
+				},
+			},
+			.tzp = &soctherm_tzp,
+		},
+	},
+};
+
+/* Only the diffs from ardbeg_soctherm_data structure */
+static struct soctherm_platform_data t132ref_v2_soctherm_data = {
+	.therm = {
+		[THERM_CPU] = {
+			.zone_enable = true,
+			.passive_delay = 1000,
+			.hotspot_offset = 10000,
+			.num_trips = 3,
+			.trips = {
+				{
+					.cdev_type = "tegra-shutdown",
+					.trip_temp = 105000,
+					.trip_type = THERMAL_TRIP_CRITICAL,
+					.upper = THERMAL_NO_LIMIT,
+					.lower = THERMAL_NO_LIMIT,
+				},
+				{
+					.cdev_type = "tegra-heavy",
+					.trip_temp = 102000,
+					.trip_type = THERMAL_TRIP_HOT,
+					.upper = THERMAL_NO_LIMIT,
+					.lower = THERMAL_NO_LIMIT,
+				},
+				{
+					.cdev_type = "cpu-balanced",
+					.trip_temp = 92000,
+					.trip_type = THERMAL_TRIP_PASSIVE,
+					.upper = THERMAL_NO_LIMIT,
+					.lower = THERMAL_NO_LIMIT,
+				},
+			},
+			.tzp = &soctherm_tzp,
+		},
+		[THERM_GPU] = {
+			.zone_enable = true,
+			.passive_delay = 1000,
+			.hotspot_offset = 5000,
+			.num_trips = 3,
+			.trips = {
+				{
+					.cdev_type = "tegra-shutdown",
+					.trip_temp = 101000,
+					.trip_type = THERMAL_TRIP_CRITICAL,
+					.upper = THERMAL_NO_LIMIT,
+					.lower = THERMAL_NO_LIMIT,
+				},
+				{
+					.cdev_type = "tegra-heavy",
+					.trip_temp = 99000,
+					.trip_type = THERMAL_TRIP_HOT,
+					.upper = THERMAL_NO_LIMIT,
+					.lower = THERMAL_NO_LIMIT,
+				},
+				{
+					.cdev_type = "gpu-balanced",
+					.trip_temp = 89000,
 					.trip_type = THERMAL_TRIP_PASSIVE,
 					.upper = THERMAL_NO_LIMIT,
 					.lower = THERMAL_NO_LIMIT,
@@ -720,10 +786,14 @@ static struct soctherm_throttle voltmon_throttle = {
 
 int __init ardbeg_soctherm_init(void)
 {
+	const int t12x_edp_temp_margin = 7000,
+		t13x_cpu_edp_temp_margin = 5000,
+		t13x_gpu_edp_temp_margin = 6000;
+	int cpu_edp_temp_margin, gpu_edp_temp_margin;
 	int cp_rev, ft_rev;
 	struct board_info pmu_board_info;
 	struct board_info board_info;
-	enum soctherm_therm_id therm_cpu;
+	enum soctherm_therm_id therm_cpu = THERM_CPU;
 
 	tegra_get_board_info(&board_info);
 
@@ -736,19 +806,29 @@ int __init ardbeg_soctherm_init(void)
 	cp_rev = tegra_fuse_calib_base_get_cp(NULL, NULL);
 	ft_rev = tegra_fuse_calib_base_get_ft(NULL, NULL);
 
-	/* Bowmore and P1761 are T132 platforms: ATE rev check (TODO) */
+	/* Bowmore and P1761 are T132 platforms */
 	if (board_info.board_id == BOARD_E1971 ||
 			board_info.board_id == BOARD_P1761 ||
 			board_info.board_id == BOARD_E1991) {
-		memcpy(&ardbeg_soctherm_data.therm[THERM_CPU],
-			&t132ref_v1_soctherm_data.therm[THERM_CPU],
-			sizeof(t132ref_v1_soctherm_data.therm[THERM_CPU]));
-		memcpy(&ardbeg_soctherm_data.therm[THERM_PLL],
-			&t132ref_v1_soctherm_data.therm[THERM_PLL],
-			sizeof(t132ref_v1_soctherm_data.therm[THERM_PLL]));
-		therm_cpu = THERM_PLL; /* override CPU zone with PLL zone */
+		cpu_edp_temp_margin = t13x_cpu_edp_temp_margin;
+		gpu_edp_temp_margin = t13x_gpu_edp_temp_margin;
+		if (!cp_rev) {
+			/* ATE rev is NEW: use v2 table */
+			ardbeg_soctherm_data.therm[THERM_CPU] =
+				t132ref_v2_soctherm_data.therm[THERM_CPU];
+			ardbeg_soctherm_data.therm[THERM_GPU] =
+				t132ref_v2_soctherm_data.therm[THERM_GPU];
+		} else {
+			/* ATE rev is Old or Mid: use PLLx sensor only */
+			ardbeg_soctherm_data.therm[THERM_CPU] =
+				t132ref_v1_soctherm_data.therm[THERM_CPU];
+			ardbeg_soctherm_data.therm[THERM_PLL] =
+				t132ref_v1_soctherm_data.therm[THERM_PLL];
+			therm_cpu = THERM_PLL; /* override CPU with PLL zone */
+		}
 	} else {
-		therm_cpu = THERM_CPU;
+		cpu_edp_temp_margin = t12x_edp_temp_margin;
+		gpu_edp_temp_margin = t12x_edp_temp_margin;
 	}
 
 	/* do this only for supported CP,FT fuses */
@@ -756,11 +836,11 @@ int __init ardbeg_soctherm_init(void)
 		tegra_platform_edp_init(
 			ardbeg_soctherm_data.therm[therm_cpu].trips,
 			&ardbeg_soctherm_data.therm[therm_cpu].num_trips,
-			7000); /* edp temperature margin */
+			cpu_edp_temp_margin);
 		tegra_platform_gpu_edp_init(
 			ardbeg_soctherm_data.therm[THERM_GPU].trips,
 			&ardbeg_soctherm_data.therm[THERM_GPU].num_trips,
-			7000);
+			gpu_edp_temp_margin);
 		tegra_add_cpu_vmax_trips(
 			ardbeg_soctherm_data.therm[therm_cpu].trips,
 			&ardbeg_soctherm_data.therm[therm_cpu].num_trips);