diff options
| author | Greg Heinrich <gheinrich@nvidia.com> | 2014-02-03 16:45:28 +0100 |
|---|---|---|
| committer | Thomas Cherry <tcherry@nvidia.com> | 2014-03-07 16:16:07 -0800 |
| commit | e421d61a7b20eb13dca6f8b3570ea19d36b63ad4 (patch) | |
| tree | 487059a9faee1eb51ed72132671ace9c19c96670 /arch/arm/mach-tegra/board-ardbeg-power.c | |
| parent | 51876644d71c25ee6c1b25b24dcbd6166aedfac4 (diff) | |
arm: tegra: ardbeg: enable OC3 throttling
This patch enables OC3 throttling on Ardbeg platform,
conditional on Bruce baseband being enabled.
Configures soc_therm with 50% throttling for CPU and
"medium_throttling" for GPU.
Configures GPIO_PK0 I/O as INPUT/PULL_DOWN.
bug 1451260
Change-Id: Ib443be161b34827cf8190b737ff15313683ce051
Signed-off-by: Greg Heinrich <gheinrich@nvidia.com>
Reviewed-on: http://git-master/r/362941
(cherry picked from commit 5f9322d9d031ce397a458553cb9b14ea98221807)
Reviewed-on: http://git-master/r/375585
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Steve Rogers <srogers@nvidia.com>
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/board-ardbeg-power.c')
| -rw-r--r-- | arch/arm/mach-tegra/board-ardbeg-power.c | 34 |
1 files changed, 32 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/board-ardbeg-power.c b/arch/arm/mach-tegra/board-ardbeg-power.c index 05023bb4c9d3..849d88f3ce91 100644 --- a/arch/arm/mach-tegra/board-ardbeg-power.c +++ b/arch/arm/mach-tegra/board-ardbeg-power.c @@ -1464,7 +1464,7 @@ static struct soctherm_platform_data ardbeg_soctherm_data = { static struct soctherm_throttle battery_oc_throttle = { .throt_mode = BRIEF, - .polarity = 1, + .polarity = SOCTHERM_ACTIVE_LOW, .priority = 100, .devs = { [THROTTLE_DEV_CPU] = { @@ -1480,7 +1480,7 @@ static struct soctherm_throttle battery_oc_throttle = { static struct soctherm_throttle voltmon_throttle = { .throt_mode = BRIEF, - .polarity = 1, + .polarity = SOCTHERM_ACTIVE_LOW, .priority = 50, .intr = true, .alarm_cnt_threshold = 100, @@ -1501,6 +1501,22 @@ static struct soctherm_throttle voltmon_throttle = { }, }; +struct soctherm_throttle baseband_throttle = { + .throt_mode = BRIEF, + .polarity = SOCTHERM_ACTIVE_HIGH, + .priority = 50, + .devs = { + [THROTTLE_DEV_CPU] = { + .enable = true, + .depth = 50, + }, + [THROTTLE_DEV_GPU] = { + .enable = true, + .throttling_depth = "medium_throttling", + }, + }, +}; + int __init ardbeg_soctherm_init(void) { s32 base_cp, shft_cp; @@ -1584,5 +1600,19 @@ int __init ardbeg_soctherm_init(void) break; } + /* enable baseband OC if Bruce modem is enabled */ + if (tegra_get_modem_id() == TEGRA_BB_BRUCE) { + /* enable baseband OC unless board has voltage comparator */ + int board_has_vc; + + board_has_vc = (pmu_board_info.board_id == BOARD_P1761) + && (pmu_board_info.fab >= BOARD_FAB_A02); + + if (!board_has_vc) + memcpy(&ardbeg_soctherm_data.throttle[THROTTLE_OC3], + &baseband_throttle, + sizeof(baseband_throttle)); + } + return tegra11_soctherm_init(&ardbeg_soctherm_data); } |