diff options
| author | Alex Frid <afrid@nvidia.com> | 2011-06-30 11:40:52 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:47:17 -0800 |
| commit | 1af45b5412cafcd3f68a6efff8df744def8ea1cd (patch) | |
| tree | e5104062eb9bb536fb6ee3069ec4b428aab80370 /arch/arm/mach-tegra/board-cardhu-memory.c | |
| parent | 4929544caf3f8288ebff375382bbc4e0b6d1e2dd (diff) | |
ARM: tegra: cardhu: Add 408MHz node to EMC DFS table
Bug 836260
Original-Change-Id: I4fb8e8eb3610676f89cb29ee0d10487c01200f95
Reviewed-on: http://git-master/r/39244
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R1edb58986433fd6cc95ddecf0ef38e8c41f81fed
Diffstat (limited to 'arch/arm/mach-tegra/board-cardhu-memory.c')
| -rw-r--r-- | arch/arm/mach-tegra/board-cardhu-memory.c | 125 |
1 files changed, 121 insertions, 4 deletions
diff --git a/arch/arm/mach-tegra/board-cardhu-memory.c b/arch/arm/mach-tegra/board-cardhu-memory.c index fab84008752a..af92de16831e 100644 --- a/arch/arm/mach-tegra/board-cardhu-memory.c +++ b/arch/arm/mach-tegra/board-cardhu-memory.c @@ -691,7 +691,7 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = { 0x000002a0, /* EMC_XM2CMDPADCTRL */ 0x0800211c, /* EMC_XM2DQSPADCTRL2 */ 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc084, /* EMC_XM2CLKPADCTRL */ + 0x77fff884, /* EMC_XM2CLKPADCTRL */ 0x01f1f108, /* EMC_XM2COMPPADCTRL */ 0x03037404, /* EMC_XM2VTTGENPADCTRL */ 0x54000007, /* EMC_XM2VTTGENPADCTRL2 */ @@ -808,7 +808,7 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = { 0x000002a0, /* EMC_XM2CMDPADCTRL */ 0x0800211c, /* EMC_XM2DQSPADCTRL2 */ 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc084, /* EMC_XM2CLKPADCTRL */ + 0x77fff884, /* EMC_XM2CLKPADCTRL */ 0x01f1f108, /* EMC_XM2COMPPADCTRL */ 0x03037404, /* EMC_XM2VTTGENPADCTRL */ 0x54000007, /* EMC_XM2VTTGENPADCTRL2 */ @@ -925,7 +925,7 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = { 0x000002a0, /* EMC_XM2CMDPADCTRL */ 0x0800211c, /* EMC_XM2DQSPADCTRL2 */ 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc084, /* EMC_XM2CLKPADCTRL */ + 0x77fff884, /* EMC_XM2CLKPADCTRL */ 0x01f1f108, /* EMC_XM2COMPPADCTRL */ 0x03037404, /* EMC_XM2VTTGENPADCTRL */ 0x54000007, /* EMC_XM2VTTGENPADCTRL2 */ @@ -967,6 +967,123 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = { }, { 0x30, /* Rev 3.0 */ + 408000, /* SDRAM frequency */ + { + 0x00000012, /* EMC_RC */ + 0x00000040, /* EMC_RFC */ + 0x0000000d, /* EMC_RAS */ + 0x00000004, /* EMC_RP */ + 0x00000002, /* EMC_R2W */ + 0x00000009, /* EMC_W2R */ + 0x00000002, /* EMC_R2P */ + 0x0000000c, /* EMC_W2P */ + 0x00000004, /* EMC_RD_RCD */ + 0x00000004, /* EMC_WR_RCD */ + 0x00000002, /* EMC_RRD */ + 0x00000001, /* EMC_REXT */ + 0x00000000, /* EMC_WEXT */ + 0x00000005, /* EMC_WDV */ + 0x00000007, /* EMC_QUSE */ + 0x00000005, /* EMC_QRST */ + 0x00000008, /* EMC_QSAFE */ + 0x0000000e, /* EMC_RDV */ + 0x00000c2e, /* EMC_REFRESH */ + 0x00000000, /* EMC_BURST_REFRESH_NUM */ + 0x0000030b, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000008, /* EMC_PDEX2WR */ + 0x00000008, /* EMC_PDEX2RD */ + 0x00000001, /* EMC_PCHG2PDEN */ + 0x00000000, /* EMC_ACT2PDEN */ + 0x00000008, /* EMC_AR2PDEN */ + 0x00000011, /* EMC_RW2PDEN */ + 0x00000046, /* EMC_TXSR */ + 0x00000200, /* EMC_TXSRDLL */ + 0x0000000a, /* EMC_TCKE */ + 0x0000000d, /* EMC_TFAW */ + 0x00000000, /* EMC_TRPAB */ + 0x00000004, /* EMC_TCLKSTABLE */ + 0x00000005, /* EMC_TCLKSTOP */ + 0x00000c6f, /* EMC_TREFBW */ + 0x00000000, /* EMC_QUSE_EXTRA */ + 0x00000006, /* EMC_FBIO_CFG6 */ + 0x00000000, /* EMC_ODT_WRITE */ + 0x00000000, /* EMC_ODT_READ */ + 0x00007088, /* EMC_FBIO_CFG5 */ + 0x001c0084, /* EMC_CFG_DIG_DLL */ + 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00014000, /* EMC_DLL_XFORM_DQS0 */ + 0x00014000, /* EMC_DLL_XFORM_DQS1 */ + 0x00014000, /* EMC_DLL_XFORM_DQS2 */ + 0x00014000, /* EMC_DLL_XFORM_DQS3 */ + 0x00014000, /* EMC_DLL_XFORM_DQS4 */ + 0x00014000, /* EMC_DLL_XFORM_DQS5 */ + 0x00014000, /* EMC_DLL_XFORM_DQS6 */ + 0x00014000, /* EMC_DLL_XFORM_DQS7 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ + 0x00020000, /* EMC_DLL_XFORM_DQ0 */ + 0x00020000, /* EMC_DLL_XFORM_DQ1 */ + 0x00020000, /* EMC_DLL_XFORM_DQ2 */ + 0x00020000, /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0, /* EMC_XM2CMDPADCTRL */ + 0x0800013d, /* EMC_XM2DQSPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL2 */ + 0x77fff884, /* EMC_XM2CLKPADCTRL */ + 0x01f1f508, /* EMC_XM2COMPPADCTRL */ + 0x03037404, /* EMC_XM2VTTGENPADCTRL */ + 0x54000007, /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8, /* EMC_XM2QUSEPADCTRL */ + 0x08000021, /* EMC_XM2DQSPADCTRL3 */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ + 0x00020000, /* EMC_ZCAL_INTERVAL */ + 0x00000100, /* EMC_ZCAL_WAIT_CNT */ + 0x017f000c, /* EMC_MRS_WAIT_CNT */ + 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_CTT */ + 0x00000000, /* EMC_CTT_DURATION */ + 0x80001941, /* EMC_DYN_SELF_REF_CONTROL */ + 0x00000006, /* MC_EMEM_ARB_CFG */ + 0x8000004a, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RP */ + 0x0000000a, /* MC_EMEM_ARB_TIMING_RC */ + 0x00000006, /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000006, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030202, /* MC_EMEM_ARB_DA_TURNS */ + 0x000e070a, /* MC_EMEM_ARB_DA_COVERS */ + 0x7547130b, /* MC_EMEM_ARB_MISC0 */ + 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ + }, + 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ + 0x00000000, /* EMC_CFG.PERIODIC_QRST */ + 0x80000731, /* Mode Register 0 */ + 0x80100002, /* Mode Register 1 */ + 0x80200008, /* Mode Register 2 */ + }, + { + 0x30, /* Rev 3.0 */ 533000, /* SDRAM frequency */ { 0x00000018, /* EMC_RC */ @@ -1042,7 +1159,7 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = { 0x000006a0, /* EMC_XM2CMDPADCTRL */ 0x0800013d, /* EMC_XM2DQSPADCTRL2 */ 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc084, /* EMC_XM2CLKPADCTRL */ + 0x77fff884, /* EMC_XM2CLKPADCTRL */ 0x01f1f508, /* EMC_XM2COMPPADCTRL */ 0x03037404, /* EMC_XM2VTTGENPADCTRL */ 0x54000007, /* EMC_XM2VTTGENPADCTRL2 */ |