ARM: tegra: cardhu: Update EMC DFS table for Hynix DDR3

Changed table format to revision 3.1; added 750MHz entry.

Bug 836260
Bug 829932

Original-Change-Id: I1e9d8db21012fc0dcb62367c3f00dc32a4d969bb
Reviewed-on: http://git-master/r/42525
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Rf27767784fa3c62f2e9e2049cf9d9cdbd67ead40

1 files changed, 138 insertions, 9 deletions

diff --git a/arch/arm/mach-tegra/board-cardhu-memory.c b/arch/arm/mach-tegra/board-cardhu-memory.c
index 15d049b95a89..43cb3f61634a 100644
--- a/arch/arm/mach-tegra/board-cardhu-memory.c
+++ b/arch/arm/mach-tegra/board-cardhu-memory.c
@@ -615,7 +615,7 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g[] = {
 
 static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = {
 	{
-		0x30,       /* Rev 3.0 */
+		0x31,       /* Rev 3.1 */
 		25500,      /* SDRAM frequency */
 		{
 			0x00000001, /* EMC_RC */
@@ -691,7 +691,7 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = {
 			0x000002a0, /* EMC_XM2CMDPADCTRL */
 			0x0800211c, /* EMC_XM2DQSPADCTRL2 */
 			0x00000000, /* EMC_XM2DQPADCTRL2 */
-			0x77fff884, /* EMC_XM2CLKPADCTRL */
+			0x77ffc084, /* EMC_XM2CLKPADCTRL */
 			0x01f1f108, /* EMC_XM2COMPPADCTRL */
 			0x03037404, /* EMC_XM2VTTGENPADCTRL */
 			0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
@@ -723,6 +723,8 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = {
 			0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
 			0x74430303, /* MC_EMEM_ARB_MISC0 */
 			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+			0xd8000000, /* EMC_FBIO_SPARE */
+			0xff00ff00, /* EMC_CFG_RSV */
 		},
 		0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
 		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
@@ -732,7 +734,7 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = {
 		0x80200008, /* Mode Register 2 */
 	},
 	{
-		0x30,       /* Rev 3.0 */
+		0x31,       /* Rev 3.1 */
 		51000,      /* SDRAM frequency */
 		{
 			0x00000002, /* EMC_RC */
@@ -808,7 +810,7 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = {
 			0x000002a0, /* EMC_XM2CMDPADCTRL */
 			0x0800211c, /* EMC_XM2DQSPADCTRL2 */
 			0x00000000, /* EMC_XM2DQPADCTRL2 */
-			0x77fff884, /* EMC_XM2CLKPADCTRL */
+			0x77ffc084, /* EMC_XM2CLKPADCTRL */
 			0x01f1f108, /* EMC_XM2COMPPADCTRL */
 			0x03037404, /* EMC_XM2VTTGENPADCTRL */
 			0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
@@ -840,6 +842,8 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = {
 			0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
 			0x73430303, /* MC_EMEM_ARB_MISC0 */
 			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+			0xd8000000, /* EMC_FBIO_SPARE */
+			0xff00ff00, /* EMC_CFG_RSV */
 		},
 		0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
 		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
@@ -849,7 +853,7 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = {
 		0x80200008, /* Mode Register 2 */
 	},
 	{
-		0x30,       /* Rev 3.0 */
+		0x31,       /* Rev 3.1 */
 		102000,     /* SDRAM frequency */
 		{
 			0x00000004, /* EMC_RC */
@@ -925,7 +929,7 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = {
 			0x000002a0, /* EMC_XM2CMDPADCTRL */
 			0x0800211c, /* EMC_XM2DQSPADCTRL2 */
 			0x00000000, /* EMC_XM2DQPADCTRL2 */
-			0x77fff884, /* EMC_XM2CLKPADCTRL */
+			0x77ffc084, /* EMC_XM2CLKPADCTRL */
 			0x01f1f108, /* EMC_XM2COMPPADCTRL */
 			0x03037404, /* EMC_XM2VTTGENPADCTRL */
 			0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
@@ -957,6 +961,8 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = {
 			0x000a0403, /* MC_EMEM_ARB_DA_COVERS */
 			0x72830504, /* MC_EMEM_ARB_MISC0 */
 			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+			0xd8000000, /* EMC_FBIO_SPARE */
+			0xff00ff00, /* EMC_CFG_RSV */
 		},
 		0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
 		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
@@ -966,7 +972,7 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = {
 		0x80200008, /* Mode Register 2 */
 	},
 	{
-		0x30,       /* Rev 3.0 */
+		0x31,       /* Rev 3.1 */
 		408000,     /* SDRAM frequency */
 		{
 			0x00000012, /* EMC_RC */
@@ -1074,6 +1080,8 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = {
 			0x000e070a, /* MC_EMEM_ARB_DA_COVERS */
 			0x7547130b, /* MC_EMEM_ARB_MISC0 */
 			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+			0x58000000, /* EMC_FBIO_SPARE */
+			0xff00ff88, /* EMC_CFG_RSV */
 		},
 		0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
 		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
@@ -1083,7 +1091,7 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = {
 		0x80200008, /* Mode Register 2 */
 	},
 	{
-		0x30,       /* Rev 3.0 */
+		0x31,       /* Rev 3.1 */
 		533000,     /* SDRAM frequency */
 		{
 			0x00000018, /* EMC_RC */
@@ -1159,7 +1167,7 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = {
 			0x000006a0, /* EMC_XM2CMDPADCTRL */
 			0x0800013d, /* EMC_XM2DQSPADCTRL2 */
 			0x00000000, /* EMC_XM2DQPADCTRL2 */
-			0x77fff884, /* EMC_XM2CLKPADCTRL */
+			0x77ffc084, /* EMC_XM2CLKPADCTRL */
 			0x01f1f508, /* EMC_XM2COMPPADCTRL */
 			0x03037404, /* EMC_XM2VTTGENPADCTRL */
 			0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
@@ -1191,6 +1199,8 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = {
 			0x0010090d, /* MC_EMEM_ARB_DA_COVERS */
 			0x7028180e, /* MC_EMEM_ARB_MISC0 */
 			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+			0x00000000, /* EMC_FBIO_SPARE */
+			0xff00ff00, /* EMC_CFG_RSV */
 		},
 		0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
 		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
@@ -1199,6 +1209,125 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = {
 		0x80100002, /* Mode Register 1 */
 		0x80200008, /* Mode Register 2 */
 	},
+	{
+		0x31,       /* Rev 3.1 */
+		750000,     /* SDRAM frequency */
+		{
+			0x00000025, /* EMC_RC */
+			0x0000007e, /* EMC_RFC */
+			0x0000001a, /* EMC_RAS */
+			0x00000009, /* EMC_RP */
+			0x00000004, /* EMC_R2W */
+			0x0000000d, /* EMC_W2R */
+			0x00000004, /* EMC_R2P */
+			0x00000013, /* EMC_W2P */
+			0x00000009, /* EMC_RD_RCD */
+			0x00000009, /* EMC_WR_RCD */
+			0x00000003, /* EMC_RRD */
+			0x00000001, /* EMC_REXT */
+			0x00000000, /* EMC_WEXT */
+			0x00000007, /* EMC_WDV */
+			0x0000000b, /* EMC_QUSE */
+			0x00000009, /* EMC_QRST */
+			0x0000000c, /* EMC_QSAFE */
+			0x00000011, /* EMC_RDV */
+			0x0000169a, /* EMC_REFRESH */
+			0x00000000, /* EMC_BURST_REFRESH_NUM */
+			0x00000608, /* EMC_PRE_REFRESH_REQ_CNT */
+			0x00000012, /* EMC_PDEX2WR */
+			0x00000012, /* EMC_PDEX2RD */
+			0x00000001, /* EMC_PCHG2PDEN */
+			0x00000000, /* EMC_ACT2PDEN */
+			0x0000000f, /* EMC_AR2PDEN */
+			0x00000018, /* EMC_RW2PDEN */
+			0x00000088, /* EMC_TXSR */
+			0x00000200, /* EMC_TXSRDLL */
+			0x00000014, /* EMC_TCKE */
+			0x00000018, /* EMC_TFAW */
+			0x00000000, /* EMC_TRPAB */
+			0x00000007, /* EMC_TCLKSTABLE */
+			0x00000008, /* EMC_TCLKSTOP */
+			0x00001860, /* EMC_TREFBW */
+			0x0000000c, /* EMC_QUSE_EXTRA */
+			0x00000004, /* EMC_FBIO_CFG6 */
+			0x00000000, /* EMC_ODT_WRITE */
+			0x00000000, /* EMC_ODT_READ */
+			0x00005088, /* EMC_FBIO_CFG5 */
+			0x40070191, /* EMC_CFG_DIG_DLL */
+			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+			0x00000008, /* EMC_DLL_XFORM_DQS0 */
+			0x00000008, /* EMC_DLL_XFORM_DQS1 */
+			0x00000008, /* EMC_DLL_XFORM_DQS2 */
+			0x00000008, /* EMC_DLL_XFORM_DQS3 */
+			0x00000008, /* EMC_DLL_XFORM_DQS4 */
+			0x00000008, /* EMC_DLL_XFORM_DQS5 */
+			0x00000008, /* EMC_DLL_XFORM_DQS6 */
+			0x00000008, /* EMC_DLL_XFORM_DQS7 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+			0x0000000c, /* EMC_DLL_XFORM_DQ0 */
+			0x0000000c, /* EMC_DLL_XFORM_DQ1 */
+			0x0000000c, /* EMC_DLL_XFORM_DQ2 */
+			0x0000000c, /* EMC_DLL_XFORM_DQ3 */
+			0x000002a0, /* EMC_XM2CMDPADCTRL */
+			0x0600013d, /* EMC_XM2DQSPADCTRL2 */
+			0x22220000, /* EMC_XM2DQPADCTRL2 */
+			0x77fff884, /* EMC_XM2CLKPADCTRL */
+			0x01f1f501, /* EMC_XM2COMPPADCTRL */
+			0x07077404, /* EMC_XM2VTTGENPADCTRL */
+			0x54000000, /* EMC_XM2VTTGENPADCTRL2 */
+			0x080001e8, /* EMC_XM2QUSEPADCTRL */
+			0x07000021, /* EMC_XM2DQSPADCTRL3 */
+			0x00000802, /* EMC_CTT_TERM_CTRL */
+			0x00020000, /* EMC_ZCAL_INTERVAL */
+			0x00000100, /* EMC_ZCAL_WAIT_CNT */
+			0x0180000c, /* EMC_MRS_WAIT_CNT */
+			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+			0x00000000, /* EMC_CTT */
+			0x00000000, /* EMC_CTT_DURATION */
+			0x8000308c, /* EMC_DYN_SELF_REF_CONTROL */
+			0x0000000c, /* MC_EMEM_ARB_CFG */
+			0x80000090, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000004, /* MC_EMEM_ARB_TIMING_RCD */
+			0x00000005, /* MC_EMEM_ARB_TIMING_RP */
+			0x00000013, /* MC_EMEM_ARB_TIMING_RC */
+			0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */
+			0x0000000b, /* MC_EMEM_ARB_TIMING_FAW */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
+			0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+			0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+			0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+			0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
+			0x00000008, /* MC_EMEM_ARB_TIMING_W2R */
+			0x08040202, /* MC_EMEM_ARB_DA_TURNS */
+			0x00160d13, /* MC_EMEM_ARB_DA_COVERS */
+			0x72ac2414, /* MC_EMEM_ARB_MISC0 */
+			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+			0xf8000000, /* EMC_FBIO_SPARE */
+			0xff00ff49, /* EMC_CFG_RSV */
+		},
+		0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
+		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+		0x00000001, /* EMC_CFG.PERIODIC_QRST */
+		0x80000d71, /* Mode Register 0 */
+		0x80100002, /* Mode Register 1 */
+		0x80200018, /* Mode Register 2 */
+	},
 };
 
 static const struct tegra_emc_table cardhu_emc_tables_k4p8g304eb[] = {