diff options
author | Ray Poudrier <rapoudrier@nvidia.com> | 2012-03-22 23:12:47 -0700 |
---|---|---|
committer | Simone Willett <swillett@nvidia.com> | 2012-04-10 16:56:38 -0700 |
commit | 1cfc6a5d40d49cd0574777b950fff89671e45f6e (patch) | |
tree | a8aca1bc8f78841bfa5d0d8ae0beac9717d69353 /arch/arm/mach-tegra/board-cardhu-memory.c | |
parent | f5c21b53486d80afd547ad5f8c35302fad04f838 (diff) |
ARM: tegra: cardhu: integrate latest mem tables
Bug 918704
Change-Id: I83bdce136df07d744c69a75a38bb5ae1d541055e
Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com>
Reviewed-on: http://git-master/r/91935
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/board-cardhu-memory.c')
-rw-r--r-- | arch/arm/mach-tegra/board-cardhu-memory.c | 454 |
1 files changed, 227 insertions, 227 deletions
diff --git a/arch/arm/mach-tegra/board-cardhu-memory.c b/arch/arm/mach-tegra/board-cardhu-memory.c index 21c98216ce77..0cd9e0066668 100644 --- a/arch/arm/mach-tegra/board-cardhu-memory.c +++ b/arch/arm/mach-tegra/board-cardhu-memory.c @@ -976,58 +976,58 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = { }, { 0x32, /* Rev 3.2 */ - 375000, /* SDRAM frequency */ + 204000, /* SDRAM frequency */ { - 0x00000011, /* EMC_RC */ - 0x0000003a, /* EMC_RFC */ - 0x0000000c, /* EMC_RAS */ - 0x00000004, /* EMC_RP */ - 0x00000003, /* EMC_R2W */ - 0x00000008, /* EMC_W2R */ - 0x00000002, /* EMC_R2P */ - 0x0000000a, /* EMC_W2P */ - 0x00000004, /* EMC_RD_RCD */ - 0x00000004, /* EMC_WR_RCD */ - 0x00000002, /* EMC_RRD */ + 0x00000009, /* EMC_RC */ + 0x00000020, /* EMC_RFC */ + 0x00000007, /* EMC_RAS */ + 0x00000002, /* EMC_RP */ + 0x00000002, /* EMC_R2W */ + 0x0000000a, /* EMC_W2R */ + 0x00000005, /* EMC_R2P */ + 0x0000000b, /* EMC_W2P */ + 0x00000002, /* EMC_RD_RCD */ + 0x00000002, /* EMC_WR_RCD */ + 0x00000003, /* EMC_RRD */ 0x00000001, /* EMC_REXT */ 0x00000000, /* EMC_WEXT */ - 0x00000004, /* EMC_WDV */ - 0x00000006, /* EMC_QUSE */ + 0x00000005, /* EMC_WDV */ + 0x00000005, /* EMC_QUSE */ 0x00000004, /* EMC_QRST */ - 0x00000008, /* EMC_QSAFE */ - 0x0000000d, /* EMC_RDV */ - 0x00000b2d, /* EMC_REFRESH */ + 0x00000009, /* EMC_QSAFE */ + 0x0000000b, /* EMC_RDV */ + 0x00000607, /* EMC_REFRESH */ 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x000002cb, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000008, /* EMC_PDEX2WR */ - 0x00000008, /* EMC_PDEX2RD */ + 0x00000181, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002, /* EMC_PDEX2WR */ + 0x00000002, /* EMC_PDEX2RD */ 0x00000001, /* EMC_PCHG2PDEN */ 0x00000000, /* EMC_ACT2PDEN */ 0x00000007, /* EMC_AR2PDEN */ 0x0000000f, /* EMC_RW2PDEN */ - 0x00000040, /* EMC_TXSR */ - 0x00000200, /* EMC_TXSRDLL */ - 0x00000009, /* EMC_TCKE */ - 0x0000000c, /* EMC_TFAW */ + 0x00000023, /* EMC_TXSR */ + 0x00000023, /* EMC_TXSRDLL */ + 0x00000004, /* EMC_TCKE */ + 0x00000007, /* EMC_TFAW */ 0x00000000, /* EMC_TRPAB */ 0x00000004, /* EMC_TCLKSTABLE */ 0x00000005, /* EMC_TCLKSTOP */ - 0x00000b6d, /* EMC_TREFBW */ - 0x00000000, /* EMC_QUSE_EXTRA */ - 0x00000006, /* EMC_FBIO_CFG6 */ + 0x00000638, /* EMC_TREFBW */ + 0x00000006, /* EMC_QUSE_EXTRA */ + 0x00000004, /* EMC_FBIO_CFG6 */ 0x00000000, /* EMC_ODT_WRITE */ 0x00000000, /* EMC_ODT_READ */ - 0x00007088, /* EMC_FBIO_CFG5 */ - 0x00200084, /* EMC_CFG_DIG_DLL */ + 0x00004288, /* EMC_FBIO_CFG5 */ + 0x004400a4, /* EMC_CFG_DIG_DLL */ 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0003c000, /* EMC_DLL_XFORM_DQS0 */ - 0x0003c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0003c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0003c000, /* EMC_DLL_XFORM_DQS3 */ - 0x0003c000, /* EMC_DLL_XFORM_DQS4 */ - 0x0003c000, /* EMC_DLL_XFORM_DQS5 */ - 0x0003c000, /* EMC_DLL_XFORM_DQS6 */ - 0x0003c000, /* EMC_DLL_XFORM_DQS7 */ + 0x00080000, /* EMC_DLL_XFORM_DQS0 */ + 0x00080000, /* EMC_DLL_XFORM_DQS1 */ + 0x00080000, /* EMC_DLL_XFORM_DQS2 */ + 0x00080000, /* EMC_DLL_XFORM_DQS3 */ + 0x00080000, /* EMC_DLL_XFORM_DQS4 */ + 0x00080000, /* EMC_DLL_XFORM_DQS5 */ + 0x00080000, /* EMC_DLL_XFORM_DQS6 */ + 0x00080000, /* EMC_DLL_XFORM_DQS7 */ 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ @@ -1044,110 +1044,110 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = { 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x00040000, /* EMC_DLL_XFORM_DQ0 */ - 0x00040000, /* EMC_DLL_XFORM_DQ1 */ - 0x00040000, /* EMC_DLL_XFORM_DQ2 */ - 0x00040000, /* EMC_DLL_XFORM_DQ3 */ + 0x00080000, /* EMC_DLL_XFORM_DQ0 */ + 0x00080000, /* EMC_DLL_XFORM_DQ1 */ + 0x00080000, /* EMC_DLL_XFORM_DQ2 */ + 0x00080000, /* EMC_DLL_XFORM_DQ3 */ 0x000002a0, /* EMC_XM2CMDPADCTRL */ - 0x0800013d, /* EMC_XM2DQSPADCTRL2 */ + 0x0800211c, /* EMC_XM2DQSPADCTRL2 */ 0x00000000, /* EMC_XM2DQPADCTRL2 */ 0x77fff884, /* EMC_XM2CLKPADCTRL */ - 0x01f1f508, /* EMC_XM2COMPPADCTRL */ + 0x01f1f108, /* EMC_XM2COMPPADCTRL */ 0x05057404, /* EMC_XM2VTTGENPADCTRL */ 0x54000007, /* EMC_XM2VTTGENPADCTRL2 */ - 0x080001e8, /* EMC_XM2QUSEPADCTRL */ - 0x08000021, /* EMC_XM2DQSPADCTRL3 */ + 0x08000168, /* EMC_XM2QUSEPADCTRL */ + 0x08000000, /* EMC_XM2DQSPADCTRL3 */ 0x00000802, /* EMC_CTT_TERM_CTRL */ 0x00020000, /* EMC_ZCAL_INTERVAL */ 0x00000100, /* EMC_ZCAL_WAIT_CNT */ - 0x0184000c, /* EMC_MRS_WAIT_CNT */ + 0x000c000c, /* EMC_MRS_WAIT_CNT */ 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ - 0x8000174b, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000005, /* MC_EMEM_ARB_CFG */ - 0x80000044, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */ + 0x00000003, /* MC_EMEM_ARB_CFG */ + 0xc0000025, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000009, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000005, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000005, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ + 0x00000005, /* MC_EMEM_ARB_TIMING_RC */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000003, /* MC_EMEM_ARB_TIMING_FAW */ 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */ 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2W */ 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030202, /* MC_EMEM_ARB_DA_TURNS */ - 0x000d0709, /* MC_EMEM_ARB_DA_COVERS */ - 0x75c6110a, /* MC_EMEM_ARB_MISC0 */ + 0x06020102, /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0505, /* MC_EMEM_ARB_DA_COVERS */ + 0x72440a06, /* MC_EMEM_ARB_MISC0 */ 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - 0x58000000, /* EMC_FBIO_SPARE */ - 0xff00ff88, /* EMC_CFG_RSV */ + 0xe8000000, /* EMC_FBIO_SPARE */ + 0xff00ff00, /* EMC_CFG_RSV */ }, 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */ 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x00000000, /* EMC_CFG.PERIODIC_QRST */ - 0x80000521, /* Mode Register 0 */ - 0x80100002, /* Mode Register 1 */ - 0x80200000, /* Mode Register 2 */ - 0x00000000, /* EMC_CFG.DYN_SELF_REF */ + 0x00000001, /* EMC_CFG.PERIODIC_QRST */ + 0x80001221, /* Mode Register 0 */ + 0x80100003, /* Mode Register 1 */ + 0x80200008, /* Mode Register 2 */ + 0x00000001, /* EMC_CFG.DYN_SELF_REF */ }, { 0x32, /* Rev 3.2 */ - 400000, /* SDRAM frequency */ + 375000, /* SDRAM frequency */ { - 0x00000012, /* EMC_RC */ - 0x00000040, /* EMC_RFC */ - 0x0000000d, /* EMC_RAS */ + 0x00000011, /* EMC_RC */ + 0x0000003a, /* EMC_RFC */ + 0x0000000c, /* EMC_RAS */ 0x00000004, /* EMC_RP */ - 0x00000002, /* EMC_R2W */ - 0x00000009, /* EMC_W2R */ + 0x00000003, /* EMC_R2W */ + 0x00000008, /* EMC_W2R */ 0x00000002, /* EMC_R2P */ - 0x0000000c, /* EMC_W2P */ + 0x0000000a, /* EMC_W2P */ 0x00000004, /* EMC_RD_RCD */ 0x00000004, /* EMC_WR_RCD */ 0x00000002, /* EMC_RRD */ 0x00000001, /* EMC_REXT */ 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x00000007, /* EMC_QUSE */ - 0x00000005, /* EMC_QRST */ + 0x00000004, /* EMC_WDV */ + 0x00000006, /* EMC_QUSE */ + 0x00000004, /* EMC_QRST */ 0x00000008, /* EMC_QSAFE */ - 0x0000000e, /* EMC_RDV */ - 0x00000c2e, /* EMC_REFRESH */ + 0x0000000d, /* EMC_RDV */ + 0x00000b2d, /* EMC_REFRESH */ 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x0000030b, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x000002cb, /* EMC_PRE_REFRESH_REQ_CNT */ 0x00000008, /* EMC_PDEX2WR */ 0x00000008, /* EMC_PDEX2RD */ 0x00000001, /* EMC_PCHG2PDEN */ 0x00000000, /* EMC_ACT2PDEN */ - 0x00000008, /* EMC_AR2PDEN */ - 0x00000011, /* EMC_RW2PDEN */ - 0x00000046, /* EMC_TXSR */ + 0x00000007, /* EMC_AR2PDEN */ + 0x0000000f, /* EMC_RW2PDEN */ + 0x00000040, /* EMC_TXSR */ 0x00000200, /* EMC_TXSRDLL */ - 0x0000000a, /* EMC_TCKE */ - 0x0000000d, /* EMC_TFAW */ + 0x00000009, /* EMC_TCKE */ + 0x0000000c, /* EMC_TFAW */ 0x00000000, /* EMC_TRPAB */ 0x00000004, /* EMC_TCLKSTABLE */ 0x00000005, /* EMC_TCLKSTOP */ - 0x00000c6f, /* EMC_TREFBW */ + 0x00000b6d, /* EMC_TREFBW */ 0x00000000, /* EMC_QUSE_EXTRA */ 0x00000006, /* EMC_FBIO_CFG6 */ 0x00000000, /* EMC_ODT_WRITE */ 0x00000000, /* EMC_ODT_READ */ 0x00007088, /* EMC_FBIO_CFG5 */ - 0x001c0084, /* EMC_CFG_DIG_DLL */ + 0x00200084, /* EMC_CFG_DIG_DLL */ 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00034000, /* EMC_DLL_XFORM_DQS0 */ - 0x00034000, /* EMC_DLL_XFORM_DQS1 */ - 0x00034000, /* EMC_DLL_XFORM_DQS2 */ - 0x00034000, /* EMC_DLL_XFORM_DQS3 */ - 0x00034000, /* EMC_DLL_XFORM_DQS4 */ - 0x00034000, /* EMC_DLL_XFORM_DQS5 */ - 0x00034000, /* EMC_DLL_XFORM_DQS6 */ - 0x00034000, /* EMC_DLL_XFORM_DQS7 */ + 0x0003c000, /* EMC_DLL_XFORM_DQS0 */ + 0x0003c000, /* EMC_DLL_XFORM_DQS1 */ + 0x0003c000, /* EMC_DLL_XFORM_DQS2 */ + 0x0003c000, /* EMC_DLL_XFORM_DQS3 */ + 0x0003c000, /* EMC_DLL_XFORM_DQS4 */ + 0x0003c000, /* EMC_DLL_XFORM_DQS5 */ + 0x0003c000, /* EMC_DLL_XFORM_DQS6 */ + 0x0003c000, /* EMC_DLL_XFORM_DQS7 */ 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ @@ -1180,28 +1180,28 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = { 0x00000802, /* EMC_CTT_TERM_CTRL */ 0x00020000, /* EMC_ZCAL_INTERVAL */ 0x00000100, /* EMC_ZCAL_WAIT_CNT */ - 0x017f000c, /* EMC_MRS_WAIT_CNT */ + 0x0184000c, /* EMC_MRS_WAIT_CNT */ 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ - 0x80001941, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000006, /* MC_EMEM_ARB_CFG */ - 0x8000004a, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x8000174b, /* EMC_DYN_SELF_REF_CONTROL */ + 0x00000005, /* MC_EMEM_ARB_CFG */ + 0x80000044, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000002, /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000a, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000006, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000006, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000009, /* MC_EMEM_ARB_TIMING_RC */ + 0x00000005, /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000005, /* MC_EMEM_ARB_TIMING_FAW */ 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ 0x06030202, /* MC_EMEM_ARB_DA_TURNS */ - 0x000e070a, /* MC_EMEM_ARB_DA_COVERS */ - 0x7547130b, /* MC_EMEM_ARB_MISC0 */ + 0x000d0709, /* MC_EMEM_ARB_DA_COVERS */ + 0x75c6110a, /* MC_EMEM_ARB_MISC0 */ 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ 0x58000000, /* EMC_FBIO_SPARE */ 0xff00ff88, /* EMC_CFG_RSV */ @@ -1209,14 +1209,14 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = { 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */ 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ 0x00000000, /* EMC_CFG.PERIODIC_QRST */ - 0x80000731, /* Mode Register 0 */ + 0x80000521, /* Mode Register 0 */ 0x80100002, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ + 0x80200000, /* Mode Register 2 */ 0x00000000, /* EMC_CFG.DYN_SELF_REF */ }, { 0x32, /* Rev 3.2 */ - 425000, /* SDRAM frequency */ + 400000, /* SDRAM frequency */ { 0x00000012, /* EMC_RC */ 0x00000040, /* EMC_RFC */ @@ -1576,19 +1576,19 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = { }, { 0x32, /* Rev 3.2 */ - 750000, /* SDRAM frequency */ + 667000, /* SDRAM frequency */ { - 0x00000025, /* EMC_RC */ - 0x0000007e, /* EMC_RFC */ - 0x0000001a, /* EMC_RAS */ - 0x00000009, /* EMC_RP */ + 0x0000001f, /* EMC_RC */ + 0x00000069, /* EMC_RFC */ + 0x00000016, /* EMC_RAS */ + 0x00000008, /* EMC_RP */ 0x00000004, /* EMC_R2W */ - 0x0000000d, /* EMC_W2R */ - 0x00000004, /* EMC_R2P */ - 0x00000013, /* EMC_W2P */ - 0x00000009, /* EMC_RD_RCD */ - 0x00000009, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ + 0x0000000c, /* EMC_W2R */ + 0x00000003, /* EMC_R2P */ + 0x00000011, /* EMC_W2P */ + 0x00000008, /* EMC_RD_RCD */ + 0x00000008, /* EMC_WR_RCD */ + 0x00000002, /* EMC_RRD */ 0x00000001, /* EMC_REXT */ 0x00000000, /* EMC_WEXT */ 0x00000007, /* EMC_WDV */ @@ -1596,29 +1596,29 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = { 0x00000009, /* EMC_QRST */ 0x0000000c, /* EMC_QSAFE */ 0x00000011, /* EMC_RDV */ - 0x0000169a, /* EMC_REFRESH */ + 0x00001412, /* EMC_REFRESH */ 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000608, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000012, /* EMC_PDEX2WR */ - 0x00000012, /* EMC_PDEX2RD */ + 0x00000504, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x0000000e, /* EMC_PDEX2WR */ + 0x0000000e, /* EMC_PDEX2RD */ 0x00000001, /* EMC_PCHG2PDEN */ 0x00000000, /* EMC_ACT2PDEN */ - 0x0000000f, /* EMC_AR2PDEN */ - 0x00000018, /* EMC_RW2PDEN */ - 0x00000088, /* EMC_TXSR */ + 0x0000000c, /* EMC_AR2PDEN */ + 0x00000016, /* EMC_RW2PDEN */ + 0x00000072, /* EMC_TXSR */ 0x00000200, /* EMC_TXSRDLL */ - 0x00000014, /* EMC_TCKE */ - 0x00000018, /* EMC_TFAW */ + 0x00000010, /* EMC_TCKE */ + 0x00000015, /* EMC_TFAW */ 0x00000000, /* EMC_TRPAB */ - 0x00000007, /* EMC_TCLKSTABLE */ - 0x00000008, /* EMC_TCLKSTOP */ - 0x00001860, /* EMC_TREFBW */ + 0x00000006, /* EMC_TCLKSTABLE */ + 0x00000007, /* EMC_TCLKSTOP */ + 0x00001453, /* EMC_TREFBW */ 0x0000000c, /* EMC_QUSE_EXTRA */ 0x00000004, /* EMC_FBIO_CFG6 */ 0x00000000, /* EMC_ODT_WRITE */ 0x00000000, /* EMC_ODT_READ */ 0x00005088, /* EMC_FBIO_CFG5 */ - 0xf0080191, /* EMC_CFG_DIG_DLL */ + 0x40070191, /* EMC_CFG_DIG_DLL */ 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ 0x00000008, /* EMC_DLL_XFORM_DQS0 */ 0x00000008, /* EMC_DLL_XFORM_DQS1 */ @@ -1644,15 +1644,15 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = { 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x0000000c, /* EMC_DLL_XFORM_DQ0 */ - 0x0000000c, /* EMC_DLL_XFORM_DQ1 */ - 0x0000000c, /* EMC_DLL_XFORM_DQ2 */ - 0x0000000c, /* EMC_DLL_XFORM_DQ3 */ + 0x00000008, /* EMC_DLL_XFORM_DQ0 */ + 0x00000008, /* EMC_DLL_XFORM_DQ1 */ + 0x00000008, /* EMC_DLL_XFORM_DQ2 */ + 0x00000008, /* EMC_DLL_XFORM_DQ3 */ 0x000002a0, /* EMC_XM2CMDPADCTRL */ 0x0600013d, /* EMC_XM2DQSPADCTRL2 */ - 0x22220000, /* EMC_XM2DQPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL2 */ 0x77fff884, /* EMC_XM2CLKPADCTRL */ - 0x01f1f501, /* EMC_XM2COMPPADCTRL */ + 0x01f1f508, /* EMC_XM2COMPPADCTRL */ 0x07077404, /* EMC_XM2VTTGENPADCTRL */ 0x54000000, /* EMC_XM2VTTGENPADCTRL2 */ 0x080001e8, /* EMC_XM2QUSEPADCTRL */ @@ -1660,43 +1660,43 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = { 0x00000802, /* EMC_CTT_TERM_CTRL */ 0x00020000, /* EMC_ZCAL_INTERVAL */ 0x00000100, /* EMC_ZCAL_WAIT_CNT */ - 0x0180000c, /* EMC_MRS_WAIT_CNT */ + 0x01d6000c, /* EMC_MRS_WAIT_CNT */ 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ - 0x8000308c, /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000c, /* MC_EMEM_ARB_CFG */ - 0x80000090, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000004, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000005, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000013, /* MC_EMEM_ARB_TIMING_RC */ - 0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000b, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RRD */ + 0x800028a5, /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a, /* MC_EMEM_ARB_CFG */ + 0x80000079, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000003, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000004, /* MC_EMEM_ARB_TIMING_RP */ + 0x00000010, /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000a, /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000a, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ 0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x0000000b, /* MC_EMEM_ARB_TIMING_WAP2PRE */ 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */ 0x00000008, /* MC_EMEM_ARB_TIMING_W2R */ 0x08040202, /* MC_EMEM_ARB_DA_TURNS */ - 0x00160d13, /* MC_EMEM_ARB_DA_COVERS */ - 0x72ac2414, /* MC_EMEM_ARB_MISC0 */ + 0x00140c10, /* MC_EMEM_ARB_DA_COVERS */ + 0x734a1f11, /* MC_EMEM_ARB_MISC0 */ 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ 0xf8000000, /* EMC_FBIO_SPARE */ - 0xff00ff49, /* EMC_CFG_RSV */ + 0xff00ff01, /* EMC_CFG_RSV */ }, 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */ 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ 0x00000001, /* EMC_CFG.PERIODIC_QRST */ - 0x80000d71, /* Mode Register 0 */ + 0x80000b71, /* Mode Register 0 */ 0x80100002, /* Mode Register 1 */ 0x80200018, /* Mode Register 2 */ 0x00000000, /* EMC_CFG.DYN_SELF_REF */ }, { 0x32, /* Rev 3.2 */ - 800000, /* SDRAM frequency */ + 750000, /* SDRAM frequency */ { 0x00000025, /* EMC_RC */ 0x0000007e, /* EMC_RFC */ @@ -1716,7 +1716,7 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = { 0x00000009, /* EMC_QRST */ 0x0000000c, /* EMC_QSAFE */ 0x00000011, /* EMC_RDV */ - 0x00001820, /* EMC_REFRESH */ + 0x0000169a, /* EMC_REFRESH */ 0x00000000, /* EMC_BURST_REFRESH_NUM */ 0x00000608, /* EMC_PRE_REFRESH_REQ_CNT */ 0x00000012, /* EMC_PDEX2WR */ @@ -1738,16 +1738,16 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = { 0x00000000, /* EMC_ODT_WRITE */ 0x00000000, /* EMC_ODT_READ */ 0x00005088, /* EMC_FBIO_CFG5 */ - 0xf0070191, /* EMC_CFG_DIG_DLL */ + 0xf0080191, /* EMC_CFG_DIG_DLL */ 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000000a, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS7 */ + 0x00000008, /* EMC_DLL_XFORM_DQS0 */ + 0x00000008, /* EMC_DLL_XFORM_DQS1 */ + 0x00000008, /* EMC_DLL_XFORM_DQS2 */ + 0x00000008, /* EMC_DLL_XFORM_DQS3 */ + 0x00000008, /* EMC_DLL_XFORM_DQS4 */ + 0x00000008, /* EMC_DLL_XFORM_DQS5 */ + 0x00000008, /* EMC_DLL_XFORM_DQS6 */ + 0x00000008, /* EMC_DLL_XFORM_DQS7 */ 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ @@ -1764,10 +1764,10 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = { 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ0 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ1 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ3 */ + 0x0000000c, /* EMC_DLL_XFORM_DQ0 */ + 0x0000000c, /* EMC_DLL_XFORM_DQ1 */ + 0x0000000c, /* EMC_DLL_XFORM_DQ2 */ + 0x0000000c, /* EMC_DLL_XFORM_DQ3 */ 0x000002a0, /* EMC_XM2CMDPADCTRL */ 0x0600013d, /* EMC_XM2DQSPADCTRL2 */ 0x22220000, /* EMC_XM2DQPADCTRL2 */ @@ -1816,66 +1816,66 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = { }, { 0x32, /* Rev 3.2 */ - 850000, /* SDRAM frequency */ + 800000, /* SDRAM frequency */ { - 0x00000028, /* EMC_RC */ - 0x00000086, /* EMC_RFC */ - 0x0000001c, /* EMC_RAS */ - 0x0000000a, /* EMC_RP */ - 0x00000006, /* EMC_R2W */ - 0x0000000f, /* EMC_W2R */ - 0x00000005, /* EMC_R2P */ - 0x00000016, /* EMC_W2P */ - 0x0000000a, /* EMC_RD_RCD */ - 0x0000000a, /* EMC_WR_RCD */ - 0x00000004, /* EMC_RRD */ + 0x00000025, /* EMC_RC */ + 0x0000007e, /* EMC_RFC */ + 0x0000001a, /* EMC_RAS */ + 0x00000009, /* EMC_RP */ + 0x00000004, /* EMC_R2W */ + 0x0000000d, /* EMC_W2R */ + 0x00000004, /* EMC_R2P */ + 0x00000013, /* EMC_W2P */ + 0x00000009, /* EMC_RD_RCD */ + 0x00000009, /* EMC_WR_RCD */ + 0x00000003, /* EMC_RRD */ 0x00000001, /* EMC_REXT */ 0x00000000, /* EMC_WEXT */ - 0x00000008, /* EMC_WDV */ - 0x0000000d, /* EMC_QUSE */ - 0x0000000b, /* EMC_QRST */ - 0x0000000b, /* EMC_QSAFE */ - 0x00000014, /* EMC_RDV */ - 0x000019a6, /* EMC_REFRESH */ + 0x00000007, /* EMC_WDV */ + 0x0000000b, /* EMC_QUSE */ + 0x00000009, /* EMC_QRST */ + 0x0000000c, /* EMC_QSAFE */ + 0x00000011, /* EMC_RDV */ + 0x00001820, /* EMC_REFRESH */ 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000669, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000004, /* EMC_PDEX2WR */ - 0x00000013, /* EMC_PDEX2RD */ + 0x00000608, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000012, /* EMC_PDEX2WR */ + 0x00000012, /* EMC_PDEX2RD */ 0x00000001, /* EMC_PCHG2PDEN */ 0x00000000, /* EMC_ACT2PDEN */ - 0x00000010, /* EMC_AR2PDEN */ - 0x0000001b, /* EMC_RW2PDEN */ - 0x00000091, /* EMC_TXSR */ + 0x0000000f, /* EMC_AR2PDEN */ + 0x00000018, /* EMC_RW2PDEN */ + 0x00000088, /* EMC_TXSR */ 0x00000200, /* EMC_TXSRDLL */ - 0x00000006, /* EMC_TCKE */ - 0x0000001a, /* EMC_TFAW */ + 0x00000014, /* EMC_TCKE */ + 0x00000018, /* EMC_TFAW */ 0x00000000, /* EMC_TRPAB */ - 0x00000008, /* EMC_TCLKSTABLE */ - 0x00000009, /* EMC_TCLKSTOP */ - 0x000019e6, /* EMC_TREFBW */ - 0x0000000e, /* EMC_QUSE_EXTRA */ + 0x00000007, /* EMC_TCLKSTABLE */ + 0x00000008, /* EMC_TCLKSTOP */ + 0x00001860, /* EMC_TREFBW */ + 0x0000000c, /* EMC_QUSE_EXTRA */ 0x00000004, /* EMC_FBIO_CFG6 */ 0x00000000, /* EMC_ODT_WRITE */ 0x00000000, /* EMC_ODT_READ */ 0x00005088, /* EMC_FBIO_CFG5 */ - 0xf0050191, /* EMC_CFG_DIG_DLL */ + 0xf0070191, /* EMC_CFG_DIG_DLL */ 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000c00a, /* EMC_DLL_XFORM_DQS0 */ + 0x0000800a, /* EMC_DLL_XFORM_DQS0 */ 0x0000000a, /* EMC_DLL_XFORM_DQS1 */ - 0x007fc008, /* EMC_DLL_XFORM_DQS2 */ - 0x007fc008, /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a, /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a, /* EMC_DLL_XFORM_DQS3 */ 0x0000000a, /* EMC_DLL_XFORM_DQS4 */ 0x0000000a, /* EMC_DLL_XFORM_DQS5 */ 0x0000000a, /* EMC_DLL_XFORM_DQS6 */ 0x0000000a, /* EMC_DLL_XFORM_DQS7 */ - 0x0000c000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000c000, /* EMC_DLL_XFORM_QUSE1 */ - 0x0000c000, /* EMC_DLL_XFORM_QUSE2 */ - 0x0000c000, /* EMC_DLL_XFORM_QUSE3 */ - 0x0000c000, /* EMC_DLL_XFORM_QUSE4 */ - 0x0000c000, /* EMC_DLL_XFORM_QUSE5 */ - 0x0000c000, /* EMC_DLL_XFORM_QUSE6 */ - 0x0000c000, /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ @@ -1899,39 +1899,39 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = { 0x07000021, /* EMC_XM2DQSPADCTRL3 */ 0x00000802, /* EMC_CTT_TERM_CTRL */ 0x00020000, /* EMC_ZCAL_INTERVAL */ - 0x00000110, /* EMC_ZCAL_WAIT_CNT */ - 0x0134000c, /* EMC_MRS_WAIT_CNT */ + 0x00000100, /* EMC_ZCAL_WAIT_CNT */ + 0x0180000c, /* EMC_MRS_WAIT_CNT */ 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ - 0x80003384, /* EMC_DYN_SELF_REF_CONTROL */ + 0x8000308c, /* EMC_DYN_SELF_REF_CONTROL */ 0x0000000c, /* MC_EMEM_ARB_CFG */ - 0x80000099, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x80000090, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000004, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000005, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000014, /* MC_EMEM_ARB_TIMING_RC */ - 0x0000000d, /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000c, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000013, /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000b, /* MC_EMEM_ARB_TIMING_FAW */ 0x00000002, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000004, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000e, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */ 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000005, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000009, /* MC_EMEM_ARB_TIMING_W2R */ - 0x09050202, /* MC_EMEM_ARB_DA_TURNS */ - 0x00190f14, /* MC_EMEM_ARB_DA_COVERS */ - 0x714d2715, /* MC_EMEM_ARB_MISC0 */ + 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000008, /* MC_EMEM_ARB_TIMING_W2R */ + 0x08040202, /* MC_EMEM_ARB_DA_TURNS */ + 0x00160d13, /* MC_EMEM_ARB_DA_COVERS */ + 0x72ac2414, /* MC_EMEM_ARB_MISC0 */ 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - 0xe8000000, /* EMC_FBIO_SPARE */ + 0xf8000000, /* EMC_FBIO_SPARE */ 0xff00ff49, /* EMC_CFG_RSV */ }, - 0x00000044, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */ 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ 0x00000001, /* EMC_CFG.PERIODIC_QRST */ - 0x80000f15, /* Mode Register 0 */ + 0x80000d71, /* Mode Register 0 */ 0x80100002, /* Mode Register 1 */ - 0x80200020, /* Mode Register 2 */ + 0x80200018, /* Mode Register 2 */ 0x00000000, /* EMC_CFG.DYN_SELF_REF */ }, { |