diff options
| author | Alex Frid <afrid@nvidia.com> | 2012-01-14 22:54:23 -0800 |
|---|---|---|
| committer | Rohan Somvanshi <rsomvanshi@nvidia.com> | 2012-01-24 10:57:58 -0800 |
| commit | 7d33bebaf50ad911bfa85668040a4ca42150ca09 (patch) | |
| tree | cf97bff611c2f330f731d83f25ce70a7c1fe919a /arch/arm/mach-tegra/board-cardhu-panel.c | |
| parent | 3a74a9a1c0f6337f5c970de4d890f8f6841dc12f (diff) | |
ARM: tegra: cardhu: Specify PLLD2 as backup clock source
Since not all possible PLLP output rates (216MHz, 408MHz or 204MHz)
can provide accurate enough pixel clock rate for cardhu panel, use
PLLD2 as backup clock source.
Bug 928260
Change-Id: I767e621606e849cb7d1976fbed198b9427660544
Reviewed-on: http://git-master/r/76034
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/76816
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/board-cardhu-panel.c')
| -rw-r--r-- | arch/arm/mach-tegra/board-cardhu-panel.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/board-cardhu-panel.c b/arch/arm/mach-tegra/board-cardhu-panel.c index 230e5f428dc0..90801b0e610d 100644 --- a/arch/arm/mach-tegra/board-cardhu-panel.c +++ b/arch/arm/mach-tegra/board-cardhu-panel.c @@ -942,6 +942,8 @@ static struct tegra_dc_out cardhu_disp1_out = { .parent_clk = "pll_p", #ifndef CONFIG_TEGRA_CARDHU_DSI + .parent_clk_backup = "pll_d2_out0", + .type = TEGRA_DC_OUT_RGB, .depth = 18, .dither = TEGRA_DC_ORDERED_DITHER, |