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authorMarcel Ziswiler <marcel.ziswiler@toradex.com>2018-09-20 18:25:03 +0200
committerMax Krummenacher <max.krummenacher@toradex.com>2018-09-27 15:26:11 +0200
commit2a1eb198705c855be56f2d237f9c99edbff167e3 (patch)
treefeb2b73a9492a3517815d98fcab562a4ccd8e3cc /arch/arm/mach-tegra/board-colibri_t20.c
parent0d0442e511396e246a5b9377f2d5fc6fde22fccb (diff)
colibri_t20: nand: add new v1.2b flashes
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
Diffstat (limited to 'arch/arm/mach-tegra/board-colibri_t20.c')
-rw-r--r--arch/arm/mach-tegra/board-colibri_t20.c84
1 files changed, 72 insertions, 12 deletions
diff --git a/arch/arm/mach-tegra/board-colibri_t20.c b/arch/arm/mach-tegra/board-colibri_t20.c
index 8471778c8b93..37188b1820b4 100644
--- a/arch/arm/mach-tegra/board-colibri_t20.c
+++ b/arch/arm/mach-tegra/board-colibri_t20.c
@@ -830,26 +830,29 @@ int __init colibri_t20_sdhci_init(void)
/* NAND */
static struct tegra_nand_chip_parms nand_chip_parms[] = {
- /* Micron MT29F4G08ABBDAH4 */
+ /*
+ * Micron MT29F4G08ABBDAH4 on Colibri T20 256MB V1.2a intermediate and
+ * Micron MT29F4G08ABBFAH4 on Colibri T20 256MB IT V1.2b
+ */
[0] = {
.vendor_id = 0x2C,
.device_id = 0xAC,
.read_id_fourth_byte = 0x15,
.capacity = 512,
.timing = {
- .trp = 12,
+ .trp = 15,
.trh = 10, /* tREH */
- .twp = 12,
+ .twp = 15,
.twh = 10,
- .tcs = 20, /* Max(tCS, tCH, tALS, tALH) */
+ .tcs = 25, /* Max(tCS, tCH, tALS, tALH) */
.twhr = 80,
- .tcr_tar_trr = 20, /* Max(tCR, tAR, tRR) */
+ .tcr_tar_trr = 30, /* Max(tCR, tAR, tRR) */
.twb = 100,
- .trp_resp = 12, /* tRP */
- .tadl = 70,
+ .trp_resp = 15, /* tRP */
+ .tadl = 100,
},
},
- /* Micron MT29F4G08ABBEAH4 */
+ /* Micron MT29F4G08ABBEAH4 on Colibri T20 256MB V1.2a new */
[1] = {
.vendor_id = 0x2C,
.device_id = 0xAC,
@@ -868,7 +871,7 @@ static struct tegra_nand_chip_parms nand_chip_parms[] = {
.tadl = 100,
},
},
- /* Micron MT29F8G08ABCBB on Colibri T20 before V1.2 */
+ /* Micron MT29F8G08ABCBB on Colibri T20 V1.1 aka old */
[2] = {
.vendor_id = 0x2C,
.device_id = 0x38,
@@ -888,7 +891,7 @@ static struct tegra_nand_chip_parms nand_chip_parms[] = {
.tadl = 70,
},
},
- /* Micron MT29F8G08ADBDAH4 */
+ /* Micron MT29F8G08ADBDAH4 on Colibri T20 512MB V1.2a intermediate */
[3] = {
.vendor_id = 0x2C,
.device_id = 0xA3,
@@ -907,7 +910,7 @@ static struct tegra_nand_chip_parms nand_chip_parms[] = {
.tadl = 70,
},
},
- /* Micron MT29F8G08ABBCA */
+ /* Micron MT29F8G08ABBCA on Colibri T20 512MB V1.2a new */
[4] = {
.vendor_id = 0x2C,
.device_id = 0xA3,
@@ -926,7 +929,7 @@ static struct tegra_nand_chip_parms nand_chip_parms[] = {
.tadl = 100,
},
},
- /* Samsung K9K8G08U0B */
+ /* Samsung K9K8G08U0B on Colibri T20 512MB 3.3V TSOP test */
[5] = {
.vendor_id = 0xec,
.device_id = 0xd3,
@@ -947,6 +950,63 @@ static struct tegra_nand_chip_parms nand_chip_parms[] = {
.tadl = 70,
},
},
+ /* Toshiba TC58NYG2S0HBAI4 on Colibri T20 256MB IT V1.2b */
+ [6] = {
+ .vendor_id = 0x98,
+ .device_id = 0xAC,
+ .read_id_fourth_byte = 0x26,
+ .capacity = 512,
+ .timing = {
+ .trp = 12,
+ .trh = 10, /* tREH */
+ .twp = 12,
+ .twh = 10,
+ .tcs = 20, /* Max(tCS, tCH, tALS, tALH) */
+ .twhr = 60,
+ .tcr_tar_trr = 25, /* Max(tCR, tAR, tRR) */
+ .twb = 100,
+ .trp_resp = 12, /* tRP */
+ .tadl = 100,
+ },
+ },
+ /* ISSI IS34MW04G084 on Colibri T20 256MB IT V1.2b */
+ [7] = {
+ .vendor_id = 0xC8,
+ .device_id = 0xAC,
+ .read_id_fourth_byte = 0x15,
+ .capacity = 512,
+ .timing = {
+ .trp = 25,
+ .trh = 15, /* tREH */
+ .twp = 25,
+ .twh = 15,
+ .tcs = 35, /* Max(tCS, tCH, tALS, tALH) */
+ .twhr = 60,
+ .tcr_tar_trr = 45, /* Max(tCR, tAR, tRR) */
+ .twb = 100,
+ .trp_resp = 25, /* tRP */
+ .tadl = 100,
+ },
+ },
+ /* Toshiba TH58NYG3S0HBAI4 on Colibri T20 512MB IT V1.2b */
+ [8] = {
+ .vendor_id = 0x98,
+ .device_id = 0xA3,
+ .read_id_fourth_byte = 0x26,
+ .capacity = 1024,
+ .timing = {
+ .trp = 12,
+ .trh = 10, /* tREH */
+ .twp = 12,
+ .twh = 10,
+ .tcs = 20, /* Max(tCS, tCH, tALS, tALH) */
+ .twhr = 60,
+ .tcr_tar_trr = 25, /* Max(tCR, tAR, tRR) */
+ .twb = 100,
+ .trp_resp = 12, /* tRP */
+ .tadl = 100,
+ },
+ },
};
struct tegra_nand_platform colibri_t20_nand_data = {