diff options
| author | Diwakar Tundlam <dtundlam@nvidia.com> | 2014-06-13 16:13:17 -0700 |
|---|---|---|
| committer | Mandar Padmawar <mpadmawar@nvidia.com> | 2014-06-19 07:33:37 -0700 |
| commit | a92fb9d984b4f45c6cec187d23086d0af7abbfd9 (patch) | |
| tree | 09e30e94e2a3b3ebc3c444788e70e292ba8bdd0f /arch/arm/mach-tegra/board-norrin-power.c | |
| parent | dbea38f8ed4302deecba1856b8ac5867bbd0f1f5 (diff) | |
arm: tegra: soctherm: fix pskip bypass program
Fix PSKIP configuration in soctherm for T132 chipset.
Bypass ramp rate only in soctherm, but program the similar
registers in ccroc the same as before as in soctherm for
correct throttling behavior.
Also added a clear comment noting the restriction of mapping
throttling_depth string and actual throttle depth configuration
in T13x due to indirect vector-based throttle selection.
Change-Id: I86635101fc61229e54b22db67f134917e6a7e0aa
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/423359
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Edward Riegelsberger <eriegels@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/board-norrin-power.c')
| -rw-r--r-- | arch/arm/mach-tegra/board-norrin-power.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/board-norrin-power.c b/arch/arm/mach-tegra/board-norrin-power.c index d3b25d96c59d..afcb16b5e830 100644 --- a/arch/arm/mach-tegra/board-norrin-power.c +++ b/arch/arm/mach-tegra/board-norrin-power.c @@ -272,6 +272,7 @@ static struct soctherm_platform_data norrin_soctherm_data = { [THROTTLE_DEV_CPU] = { .enable = true, .depth = 80, + /* see @PSKIP_CONFIG_NOTE in board-ardbeg-power.c */ .throttling_depth = "heavy_throttling", }, [THROTTLE_DEV_GPU] = { |