diff options
| author | Prashant Gaikwad <pgaikwad@nvidia.com> | 2011-11-01 18:16:47 +0530 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:49:43 -0800 |
| commit | 9a975335313dcb2c024d0ee243e44f02e09217c5 (patch) | |
| tree | f887f6999f0b74514c8153a53603d92c75da08e3 /arch/arm/mach-tegra/board-whistler-baseband.c | |
| parent | 1727f1ae8095d5c66b853abe8d1d5ab775470b5c (diff) | |
arm: tegra: clock: Change parent and init values
pll_m initialized to 0 so that it stays at the frequency configured
by BCT.
For AP25 pll_m runs at 760MHz. Peripherals connected to pll_m and
running at frequency not multiple of 760MHz switched to pll_c.
Bug 892505
Change-Id: Ie6abb47c4fac6d808aab5ed13a6b049c42126588
Reviewed-on: http://git-master/r/61491
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: Rcbbad7a6d277b7800e8e75962b96d533148fe1eb
Diffstat (limited to 'arch/arm/mach-tegra/board-whistler-baseband.c')
| -rw-r--r-- | arch/arm/mach-tegra/board-whistler-baseband.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/mach-tegra/board-whistler-baseband.c b/arch/arm/mach-tegra/board-whistler-baseband.c index f483b5d9a96c..1d3cc7c1f222 100644 --- a/arch/arm/mach-tegra/board-whistler-baseband.c +++ b/arch/arm/mach-tegra/board-whistler-baseband.c @@ -28,20 +28,20 @@ MODULE_PARM_DESC(baseband_type, "baseband type"); static struct tegra_clk_init_table u3xx_clk[] = { /* spi slave controller clock @ 4 x 13 Mhz interface clock */ - { "sbc1", "pll_m", 52000000, true}, + { "sbc1", "pll_c", 52000000, true}, { NULL, NULL, 0, 0}, }; static struct tegra_clk_init_table n731_clk[] = { /* spi master controller clock @ 4 x 12 Mhz interface clock */ - { "sbc1", "pll_m", 48000000, true}, + { "sbc1", "pll_c", 48000000, true}, { NULL, NULL, 0, 0}, }; static struct tegra_clk_init_table spi_loopback_clk[] = { /* spi slave / master controller clocks @ 4 x max interface clock */ - { "sbc1", "pll_m", 60000000, true}, - { "sbc2", "pll_m", 60000000, true}, + { "sbc1", "pll_c", 60000000, true}, + { "sbc2", "pll_c", 60000000, true}, { NULL, NULL, 0, 0}, }; |