diff options
author | Alex Frid <afrid@nvidia.com> | 2012-04-21 20:26:19 -0700 |
---|---|---|
committer | Simone Willett <swillett@nvidia.com> | 2012-04-26 15:00:06 -0700 |
commit | 4b243bb389f7eecc0d2d50a13b2017d13c567724 (patch) | |
tree | aa2844917342ec4263bf222f05eb6eb95c8ef6ca /arch/arm/mach-tegra/common.c | |
parent | f61271a07333c0177346716e9a85da2dfea3f73e (diff) |
ARM: tegra: clock: Move SCLK shared users initialization
Moved SCLK shared users initialization from silicon only section
of init table to common silicon/emulation section - there is no
reason to limit this settings to silicon only.
Change-Id: Ib1aa1bd3f98008b6584222e6c49f0825d635b8bd
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/98104
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/common.c')
-rw-r--r-- | arch/arm/mach-tegra/common.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index 779897729c9d..98fb3dcfa95f 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -186,14 +186,7 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = { { "sclk", "pll_p_out4", 102000000, true }, { "hclk", "sclk", 102000000, true }, { "pclk", "hclk", 51000000, true }, - { "wake.sclk", NULL, 40000000, true }, - { "sbc5.sclk", NULL, 40000000, false}, - { "sbc6.sclk", NULL, 40000000, false}, #endif - { "sbc1.sclk", NULL, 40000000, false}, - { "sbc2.sclk", NULL, 40000000, false}, - { "sbc3.sclk", NULL, 40000000, false}, - { "sbc4.sclk", NULL, 40000000, false}, #else { "pll_p", NULL, 216000000, true }, { "pll_p_out1", "pll_p", 28800000, false }, @@ -214,7 +207,14 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = { { "sdmmc1", "pll_p", 48000000, false}, { "sdmmc3", "pll_p", 48000000, false}, { "sdmmc4", "pll_p", 48000000, false}, + { "sbc1.sclk", NULL, 40000000, false}, + { "sbc2.sclk", NULL, 40000000, false}, + { "sbc3.sclk", NULL, 40000000, false}, + { "sbc4.sclk", NULL, 40000000, false}, #ifndef CONFIG_ARCH_TEGRA_2x_SOC + { "sbc5.sclk", NULL, 40000000, false}, + { "sbc6.sclk", NULL, 40000000, false}, + { "wake.sclk", NULL, 40000000, true }, { "cbus", "pll_c", 416000000, false }, { "pll_c_out1", "pll_c", 208000000, false }, { "mselect", "pll_p", 102000000, true }, |