diff options
| author | Alex Frid <afrid@nvidia.com> | 2011-08-23 22:52:42 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:48:47 -0800 |
| commit | 5a8cb95d768cfd40252cf3b1cd15a97f52db5143 (patch) | |
| tree | d2b2c7f103e8ca0c189dbfe5d3adf355bd3912fb /arch/arm/mach-tegra/cpu-tegra3.c | |
| parent | e06d79129a87936fc074afc1f3da3c9e5c4cf194 (diff) | |
ARM: tegra: power: Tune Tegra3 hotplug algorithm
- Account for EDP affect on total available MIPS when bringing on-line
(removing off-line) new cpu core. Add multi-core overhead (in percent)
as a parameter - set by default to 10%.
- Add balance level parameter: level value (in percent) defines minimum
speed ratio used by hotplug algorithm to determine if current CPU cores
are balanced, so that another core may be brought on-line. By default
set to 75%
Added tunables:
/sys/module/cpu_tegra3/parameters/mp_overhead
/sys/module/cpu_tegra3/parameters/balance_level
Bug 865176
Bug 867186
Original-Change-Id: I6f2e175e0b5ed14c4b85794949c1e65d0e7f4a36
Reviewed-on: http://git-master/r/49772
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Tested-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Rebase-Id: Rcfefb570c30bf78f6eae155c3f3f7547ac64f128
Diffstat (limited to 'arch/arm/mach-tegra/cpu-tegra3.c')
| -rw-r--r-- | arch/arm/mach-tegra/cpu-tegra3.c | 17 |
1 files changed, 14 insertions, 3 deletions
diff --git a/arch/arm/mach-tegra/cpu-tegra3.c b/arch/arm/mach-tegra/cpu-tegra3.c index 9dfa40dcef67..c55cdcc748ed 100644 --- a/arch/arm/mach-tegra/cpu-tegra3.c +++ b/arch/arm/mach-tegra/cpu-tegra3.c @@ -62,6 +62,12 @@ static unsigned int idle_bottom_freq; module_param(idle_top_freq, uint, 0644); module_param(idle_bottom_freq, uint, 0644); +static int mp_overhead = 10; +module_param(mp_overhead, int, 0644); + +static int balance_level = 75; +module_param(balance_level, int, 0644); + static struct clk *cpu_clk; static struct clk *cpu_g_clk; static struct clk *cpu_lp_clk; @@ -182,16 +188,21 @@ enum { TEGRA_CPU_SPEED_SKEWED, }; -static int tegra_cpu_speed_balance(void) +static noinline int tegra_cpu_speed_balance(void) { unsigned long highest_speed = tegra_cpu_highest_speed(); + unsigned long balanced_speed = highest_speed * balance_level / 100; + unsigned long skewed_speed = balanced_speed / 2; + unsigned int nr_cpus = num_online_cpus(); /* balanced: freq targets for all CPUs are above 50% of highest speed biased: freq target for at least one CPU is below 50% threshold skewed: freq targets for at least 2 CPUs are below 25% threshold */ - if (tegra_count_slow_cpus(highest_speed / 4) >= 2) + if ((tegra_count_slow_cpus(skewed_speed) >= 2) || + tegra_cpu_edp_favor_down(nr_cpus, mp_overhead)) return TEGRA_CPU_SPEED_SKEWED; - else if (tegra_count_slow_cpus(highest_speed / 2) >= 1) + else if ((tegra_count_slow_cpus(balanced_speed) >= 1) || + (!tegra_cpu_edp_favor_up(nr_cpus, mp_overhead))) return TEGRA_CPU_SPEED_BIASED; return TEGRA_CPU_SPEED_BALANCED; } |