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authorAlex Frid <afrid@nvidia.com>2011-04-22 19:41:41 -0700
committerDan Willemsen <dwillemsen@nvidia.com>2011-11-30 21:42:34 -0800
commitb6cc102522fececf5987c4b38ebc45c56ccd15b3 (patch)
treee52dbf9a3e0068d87b41db98c058e70a53d40407 /arch/arm/mach-tegra/cpu-tegra3.c
parent6a1aa24e805fabf26efa11b2af0f0183ab1aeda4 (diff)
ARM: tegra: clock: Clip Tegra3 CPU mode rate limits
Made sure Tegra3 LP CPU mode maximum rate, and G CPU mode minimum rate are clipped to the entries in cpufreq scaling table. Original-Change-Id: I4c82b65be3a8680edbb501041a7158d1a7fbbd07 Reviewed-on: http://git-master/r/29703 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R99b548e992c80e4850e6d7f9443db8f7d7134956
Diffstat (limited to 'arch/arm/mach-tegra/cpu-tegra3.c')
-rw-r--r--arch/arm/mach-tegra/cpu-tegra3.c8
1 files changed, 2 insertions, 6 deletions
diff --git a/arch/arm/mach-tegra/cpu-tegra3.c b/arch/arm/mach-tegra/cpu-tegra3.c
index acd6889e54f7..84ddc4ffb626 100644
--- a/arch/arm/mach-tegra/cpu-tegra3.c
+++ b/arch/arm/mach-tegra/cpu-tegra3.c
@@ -37,7 +37,6 @@
#include "clock.h"
#define INITIAL_STATE TEGRA_HP_DISABLED
-#define IDLE_HYSTERESIS 100000
#define UP2G0_DELAY_MS 200
#define UP2Gn_DELAY_MS 1000
#define DOWN_DELAY_MS 2000
@@ -62,8 +61,6 @@ static unsigned int idle_bottom_freq;
module_param(idle_top_freq, uint, 0644);
module_param(idle_bottom_freq, uint, 0644);
-static unsigned int lpcpu_max_freq;
-
static struct clk *cpu_clk;
static struct clk *cpu_g_clk;
static struct clk *cpu_lp_clk;
@@ -340,9 +337,8 @@ int tegra_auto_hotplug_init(struct mutex *cpu_lock)
if (IS_ERR(cpu_clk) || IS_ERR(cpu_g_clk) || IS_ERR(cpu_lp_clk))
return -ENOENT;
- lpcpu_max_freq = clk_get_max_rate(cpu_lp_clk) / 1000;
- idle_top_freq = lpcpu_max_freq;
- idle_bottom_freq = idle_top_freq - IDLE_HYSTERESIS;
+ idle_top_freq = clk_get_max_rate(cpu_lp_clk) / 1000;
+ idle_bottom_freq = clk_get_min_rate(cpu_g_clk) / 1000;
up2g0_delay = msecs_to_jiffies(UP2G0_DELAY_MS);
up2gn_delay = msecs_to_jiffies(UP2Gn_DELAY_MS);