diff options
| author | Bo Yan <byan@nvidia.com> | 2012-10-24 17:46:05 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 12:40:13 -0700 |
| commit | 41ba41f06ce3cae98ffa03481affc003f8caa5a4 (patch) | |
| tree | ded536586f681f0acb41d11f27d10a2c5497b3ca /arch/arm/mach-tegra/cpuidle-t11x.c | |
| parent | 7fe2e4f2899cd0059ea9a2fc15a5d75a4f0bbe1a (diff) | |
ARM: tegra: restructure cpuidle utility functions
As more and more chips are supported, the conditional compilation
flags in cpuidle.h also grows, this is becoming unwieldy and
cumbersome. Let each chip register its own set of functions can
alleviate this problem.
Change-Id: I033d7aeb7a46869783a5c78058869920d81d070b
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/147420
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
Rebase-Id: R1a350795453ebdbebad3f61a7f24e7f6a9eb4180
Diffstat (limited to 'arch/arm/mach-tegra/cpuidle-t11x.c')
| -rw-r--r-- | arch/arm/mach-tegra/cpuidle-t11x.c | 34 |
1 files changed, 22 insertions, 12 deletions
diff --git a/arch/arm/mach-tegra/cpuidle-t11x.c b/arch/arm/mach-tegra/cpuidle-t11x.c index e5fc0a770b76..4290b3135080 100644 --- a/arch/arm/mach-tegra/cpuidle-t11x.c +++ b/arch/arm/mach-tegra/cpuidle-t11x.c @@ -452,18 +452,6 @@ bool tegra11x_idle_lp2(struct cpuidle_device *dev, return entered_lp2; } -int tegra11x_cpuidle_init_soc(void) -{ - int i; - - cpu_clk_for_dvfs = tegra_get_clock_by_name("cpu_g"); - - for (i = 0; i < ARRAY_SIZE(lp2_exit_latencies); i++) - lp2_exit_latencies[i] = tegra_lp2_exit_latency; - - return 0; -} - #ifdef CONFIG_DEBUG_FS int tegra11x_lp2_debug_show(struct seq_file *s, void *data) { @@ -553,3 +541,25 @@ int tegra11x_lp2_debug_show(struct seq_file *s, void *data) return 0; } #endif + +int __init tegra11x_cpuidle_init_soc(struct tegra_cpuidle_ops *idle_ops) +{ + int i; + struct tegra_cpuidle_ops ops = { + tegra11x_idle_lp2, + tegra11x_cpu_idle_stats_lp2_ready, + tegra11x_cpu_idle_stats_lp2_time, + tegra11x_lp2_is_allowed, +#ifdef CONFIG_DEBUG_FS + tegra11x_lp2_debug_show +#endif + }; + + cpu_clk_for_dvfs = tegra_get_clock_by_name("cpu_g"); + + for (i = 0; i < ARRAY_SIZE(lp2_exit_latencies); i++) + lp2_exit_latencies[i] = tegra_lp2_exit_latency; + + *idle_ops = ops; + return 0; +} |