diff options
| author | Bo Yan <byan@nvidia.com> | 2012-10-12 11:58:30 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 12:38:38 -0700 |
| commit | 7e9b2c897a96e12f52fdc2e715290d41652d40d1 (patch) | |
| tree | ba035ef7094b3560bbacf8cf6ab06ddff360a73e /arch/arm/mach-tegra/cpuidle-t11x.c | |
| parent | 63c52211c20d6ce2adad9d4f19968f924e5cf3fb (diff) | |
ARM: tegra11x: Control power gating of each CPU
Currently, LP2 can be enabled or disabled for either CPU0 or CPUn,
this is good for T30, but for T114, CPU0 is no different from any
other CPUs in terms of hardware power management support. Add
finer control so that power gating can be enabled or disabled for
any individual CPU in fast cluster.
The control is done through sysfs interface. The node
"cpu_power_gating_in_idle" is a CPU mask. the 5 LSB represent 5
CPUs. bit 0 is for CPU0, bit 1 is for CPU1, bit 2 is for CPU2,
bit 3 is for CPU3. By default the mask is set for all CPUs. Writing
a '1' to bit n enables power gating of CPUn. any other bits are not
used. The special case is bit 4, which controls the single CPU in
slow cluster.
For example, to enable power gating for all CPUs in fast cluster,
just write a "15" to that sysfs node. To disable power gating for
all CPUs, write a "0". To enable LP2 for slow CPU, write 0x10 to
that node.
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/144136
(cherry picked from commit bbfd7d15eba22492d56831e4db1181128ffa56ae)
Change-Id: I12299718d286f51d8340c0258cbd1265f3212655
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146485
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Rebase-Id: Ra21713c217770922349b19cf5a27fcd41b5a8dcc
Diffstat (limited to 'arch/arm/mach-tegra/cpuidle-t11x.c')
| -rw-r--r-- | arch/arm/mach-tegra/cpuidle-t11x.c | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/arch/arm/mach-tegra/cpuidle-t11x.c b/arch/arm/mach-tegra/cpuidle-t11x.c index 56281551488c..4d51a1674857 100644 --- a/arch/arm/mach-tegra/cpuidle-t11x.c +++ b/arch/arm/mach-tegra/cpuidle-t11x.c @@ -77,11 +77,8 @@ static s64 tegra_cpu_wake_by_time[4] = { LLONG_MAX, LLONG_MAX, LLONG_MAX, LLONG_MAX }; #endif -static bool lp2_0_in_idle = true; -module_param(lp2_0_in_idle, bool, 0644); - -static bool lp2_n_in_idle = true; -module_param(lp2_n_in_idle, bool, 0644); +static ulong cpu_power_gating_in_idle __read_mostly = 0x1f; +module_param(cpu_power_gating_in_idle, ulong, 0644); static bool slow_cluster_power_gating_noncpu __read_mostly; module_param(slow_cluster_power_gating_noncpu, bool, 0644); @@ -150,7 +147,8 @@ bool tegra11x_lp2_is_allowed(struct cpuidle_device *dev, { s64 request; - if ((!lp2_0_in_idle && !dev->cpu) || (!lp2_n_in_idle && dev->cpu)) + if (!cpumask_test_cpu(cpu_number(dev->cpu), + to_cpumask(&cpu_power_gating_in_idle))) return false; request = ktime_to_us(tick_nohz_get_sleep_length()); |