diff options
| author | Bo Yan <byan@nvidia.com> | 2012-10-16 19:10:03 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 12:39:02 -0700 |
| commit | e7a66f217260ffc840fc580a9236476fea9e73af (patch) | |
| tree | e07ddd3f5f894b8c81c39a32dbca227c2675298e /arch/arm/mach-tegra/cpuidle-t11x.c | |
| parent | fc19f13091b55e5657bcf00f580f5e6cd0a02469 (diff) | |
ARM: tegra11x: residency time for different LP2 mode
Select CPU partition power gating only, non-CPU power gating, or
rail gating based on the required minimum residency and requested
sleep length.
The minimum residency for non-cpu power gating and rail-gating are
arbitrarily set in this change, they have to be characterized.
The minimum residency for non-cpu power gating shall always be
less than the minimu residency for rail gating.
Also fix a bug that prevents rail-gating
Change-Id: Icc646061f0fb47662fa74e77c6ae6b5d5da1444a
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/146640
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
Rebase-Id: Rd2f8f5583057310c04bf0ea1d1bd8cdbbd15a9a6
Diffstat (limited to 'arch/arm/mach-tegra/cpuidle-t11x.c')
| -rw-r--r-- | arch/arm/mach-tegra/cpuidle-t11x.c | 18 |
1 files changed, 11 insertions, 7 deletions
diff --git a/arch/arm/mach-tegra/cpuidle-t11x.c b/arch/arm/mach-tegra/cpuidle-t11x.c index f841cbcf7c98..a9c91d14ec94 100644 --- a/arch/arm/mach-tegra/cpuidle-t11x.c +++ b/arch/arm/mach-tegra/cpuidle-t11x.c @@ -272,7 +272,10 @@ static bool tegra_cpu_cluster_power_down(struct cpuidle_device *dev, tegra_dvfs_rail_off(tegra_cpu_rail, entry_time); flag = (fast_cluster_power_down_mode << TEGRA_POWER_CLUSTER_PART_SHIFT) - && TEGRA_POWER_CLUSTER_PART_MASK; + & TEGRA_POWER_CLUSTER_PART_MASK; + if ((request < tegra_min_residency_crail()) && + (flag != TEGRA_POWER_CLUSTER_PART_MASK)) + flag = TEGRA_POWER_CLUSTER_PART_NONCPU; } if (tegra_idle_lp2_last(sleep_time, flag) == 0) @@ -423,18 +426,19 @@ bool tegra11x_idle_lp2(struct cpuidle_device *dev, tegra_set_cpu_in_lp2(dev->cpu); cpu_gating_only = (((fast_cluster_power_down_mode << TEGRA_POWER_CLUSTER_PART_SHIFT) - && TEGRA_POWER_CLUSTER_PART_MASK) == 0); + & TEGRA_POWER_CLUSTER_PART_MASK) == 0); if (is_lp_cluster()) { - if (slow_cluster_power_gating_noncpu) - power_gating_cpu_only = false; + if (slow_cluster_power_gating_noncpu && + (request > tegra_min_residency_noncpu())) + power_gating_cpu_only = false; else power_gating_cpu_only = true; } else if (!cpu_gating_only && - (dev->cpu == 0) && (num_online_cpus() == 1) && - tegra_rail_off_is_allowed()) - power_gating_cpu_only = false; + tegra_rail_off_is_allowed() && + (request > tegra_min_residency_noncpu())) + power_gating_cpu_only = false; else power_gating_cpu_only = true; |