diff options
| author | sreenivasulu velpula <svelpula@nvidia.com> | 2014-07-18 15:03:40 +0530 |
|---|---|---|
| committer | Winnie Hsu <whsu@nvidia.com> | 2014-10-27 12:52:43 -0700 |
| commit | 4d44978f208f23fde7feef510b5490ee11335298 (patch) | |
| tree | b5ad2e34100c8e525d6b03bb0dbd7983d001cc8a /arch/arm/mach-tegra/dvfs.h | |
| parent | 982f479a7a11fb0aeb997bbe001d48f983e9c3f3 (diff) | |
arm: t12: clock: Change use_dfll behaviour
- If CONFIG_TEGRA_USE_DFLL_RANGE is set to '3'
then do not allow use_dfll sysfs to control
dfll range.
AND
during kernel init also, by default dfll
range becomes 0.
Bug 1563635
Change-Id: I886a6ca365a1ee0fd7619312eca1ccd17d73222b
Signed-off-by: sreenivasulu velpula <svelpula@nvidia.com>
Reviewed-on: http://git-master/r/439769
(cherry picked from commit ce3cd984f88d19f5d929c0acbe509486fddcb8bc)
Reviewed-on: http://git-master/r/559391
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Tested-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/dvfs.h')
| -rw-r--r-- | arch/arm/mach-tegra/dvfs.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/dvfs.h b/arch/arm/mach-tegra/dvfs.h index 16d705fb9ad6..c891786c642c 100644 --- a/arch/arm/mach-tegra/dvfs.h +++ b/arch/arm/mach-tegra/dvfs.h @@ -124,12 +124,23 @@ struct dvfs_rail { const char *version; }; +/* + * dfll_range - + * DFLL_RANGE_NONE : DFLL is not used + * DFLL_RANGE_ALL_RATES : DFLL is is used for all CPU rates + * DFLL_RANGE_HIGH_RATES : DFLL is used only for high rates + * above crossover with PLL dvfs curve + */ enum dfll_range { DFLL_RANGE_NONE = 0, DFLL_RANGE_ALL_RATES, DFLL_RANGE_HIGH_RATES, }; +/* DFLL usage is under thermal cooling device control */ +#define TEGRA_USE_DFLL_CDEV_CNTRL 3 + +/* DVFS settings specific for DFLL clock source */ struct dvfs_dfll_data { u32 tune0; u32 tune0_high_mv; @@ -279,6 +290,7 @@ int tegra_dvfs_replace_voltage_table(struct dvfs *d, const int *new_millivolts); int tegra_dvfs_dfll_mode_set(struct dvfs *d, unsigned long rate); int tegra_dvfs_dfll_mode_clear(struct dvfs *d, unsigned long rate); +int tegra_clk_dfll_range_control(enum dfll_range use_dfll); struct tegra_cooling_device *tegra_dvfs_get_cpu_vmax_cdev(void); struct tegra_cooling_device *tegra_dvfs_get_cpu_vmin_cdev(void); |