diff options
| author | Alex Frid <afrid@nvidia.com> | 2013-09-12 20:15:41 -0700 |
|---|---|---|
| committer | Ajay Nandakumar <anandakumarm@nvidia.com> | 2013-10-03 19:17:36 +0530 |
| commit | d2324dea6f3ccb23d06946e6b2c4ede6d7a5036f (patch) | |
| tree | 8814d3c35758784207ca468981847eeaebcabe49 /arch/arm/mach-tegra/dvfs.h | |
| parent | e41404be5e5c80f01fa13932eaa0f0c6a21b3d1e (diff) | |
ARM: tegra: dvfs: Add dvfs thermal dependency
Added temperature dependency to dynamic voltage scaling. When thermal
dvfs table is installed for the particular clock, voltage required to
run at any frequency is no longer assumed constant (i.e., worst case)
across entire operational temperature range, but determined according
to temperature index set by thermal dvfs cooling device.
The following limitations are enforced by current implementation:
- thermal dvfs is applied only when rail is in pll mode (in dfll mode
voltage on temperature dependency is taken care of by dfll h/w).
- tabulated voltages at any temperature must increase monotonically
with frequency (monotonicity is not expected at iso frequency across
temperature ranges).
- voltage for any frequency/temperature combination must be within the
respective rail minimum/maximum limits
- thermal dvfs is supported, for now, only on GPU clocks
Bug 1273253
Change-Id: I4cf2ff1ae862c32c2d2fc57b9b4c98e316539024
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/278103
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
(cherry picked from commit e0baf0bf9a692894e49c4d59c15a52f2fd405aa6)
Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/dvfs.h')
| -rw-r--r-- | arch/arm/mach-tegra/dvfs.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/dvfs.h b/arch/arm/mach-tegra/dvfs.h index b41f64e4224b..8698781dbace 100644 --- a/arch/arm/mach-tegra/dvfs.h +++ b/arch/arm/mach-tegra/dvfs.h @@ -234,6 +234,8 @@ struct dvfs_rail *tegra_dvfs_get_rail_by_name(const char *reg_id); int tegra_dvfs_predict_millivolts(struct clk *c, unsigned long rate); int tegra_dvfs_predict_millivolts_pll(struct clk *c, unsigned long rate); int tegra_dvfs_predict_millivolts_dfll(struct clk *c, unsigned long rate); +const int *tegra_dvfs_get_millivolts_pll(struct dvfs *d); + int tegra_dvfs_core_cap_level_apply(int level); int tegra_dvfs_alt_freqs_set(struct dvfs *d, unsigned long *alt_freqs); int tegra_cpu_dvfs_alter(int edp_thermal_index, const cpumask_t *cpus, @@ -251,6 +253,10 @@ void tegra_dvfs_rail_init_vmin_thermal_profile( void tegra_dvfs_rail_init_vmax_thermal_profile( int *therm_trips_table, int *therm_caps_table, struct dvfs_rail *rail, struct dvfs_dfll_data *d); +int tegra_dvfs_rail_init_thermal_dvfs_trips( + int *therm_trips_table, struct dvfs_rail *rail); +int tegra_dvfs_init_thermal_dvfs_voltages( + int *millivolts, int freqs_num, int ranges_num, struct dvfs *d); int tegra_dvfs_rail_dfll_mode_set_cold(struct dvfs_rail *rail); #ifdef CONFIG_ARCH_TEGRA_12x_SOC |