diff options
| author | Colin Cross <ccross@android.com> | 2011-04-07 14:58:11 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:37:04 -0800 |
| commit | ca6558b55469df31c0ce3eb3a4932e397040a8cf (patch) | |
| tree | 48941c3468302a5a0c5f5bdd307e30595e670e26 /arch/arm/mach-tegra/fiq.c | |
| parent | 6d8630a96ba0ff7ee741b07c47543866c3e2498e (diff) | |
ARM: tegra: fiq: Access registers directly
Change-Id: Ia10f65ed00ade7298612ae3c8e4c6255c1a5ee7e
Diffstat (limited to 'arch/arm/mach-tegra/fiq.c')
| -rw-r--r-- | arch/arm/mach-tegra/fiq.c | 55 |
1 files changed, 52 insertions, 3 deletions
diff --git a/arch/arm/mach-tegra/fiq.c b/arch/arm/mach-tegra/fiq.c index d5470169b553..bc1e9c294114 100644 --- a/arch/arm/mach-tegra/fiq.c +++ b/arch/arm/mach-tegra/fiq.c @@ -27,10 +27,59 @@ #include <mach/iomap.h> #include <mach/fiq.h> -#include <mach/legacy_irq.h> #include "board.h" +#define ICTLR_CPU_IER 0x20 +#define ICTLR_CPU_IER_SET 0x24 +#define ICTLR_CPU_IER_CLR 0x28 +#define ICTLR_CPU_IEP_CLASS 0x2C + +#define FIRST_LEGACY_IRQ 32 + +static void __iomem *ictlr_reg_base[] = { + IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE), + IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE), + IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE), + IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE), +}; + +static void tegra_legacy_select_fiq(unsigned int irq, bool fiq) +{ + void __iomem *base; + pr_debug("%s: %d\n", __func__, irq); + + irq -= 32; + base = ictlr_reg_base[irq>>5]; + writel(fiq << (irq & 31), base + ICTLR_CPU_IEP_CLASS); +} + +static void tegra_fiq_mask(struct irq_data *d) +{ + void __iomem *base; + int leg_irq; + + if (d->irq < FIRST_LEGACY_IRQ) + return; + + leg_irq = d->irq - FIRST_LEGACY_IRQ; + base = ictlr_reg_base[leg_irq >> 5]; + writel(1 << (leg_irq & 31), base + ICTLR_CPU_IER_CLR); +} + +static void tegra_fiq_unmask(struct irq_data *d) +{ + void __iomem *base; + int leg_irq; + + if (d->irq < FIRST_LEGACY_IRQ) + return; + + leg_irq = d->irq - FIRST_LEGACY_IRQ; + base = ictlr_reg_base[leg_irq >> 5]; + writel(1 << (leg_irq & 31), base + ICTLR_CPU_IER_SET); +} + void tegra_fiq_enable(int irq) { void __iomem *base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100); @@ -40,11 +89,11 @@ void tegra_fiq_enable(int irq) val |= 2; /* enableNS */ writel(val, base + GIC_CPU_CTRL); tegra_legacy_select_fiq(irq, true); - tegra_legacy_unmask_irq(irq); + tegra_fiq_unmask(irq); } void tegra_fiq_disable(int irq) { - tegra_legacy_mask_irq(irq); + tegra_fiq_mask(irq); tegra_legacy_select_fiq(irq, false); } |