diff options
| author | Diwakar Tundlam <dtundlam@nvidia.com> | 2011-05-18 16:58:03 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:42:41 -0800 |
| commit | 7a3a6cecdf050e0d988b5ab8e32d94e8d4ea4bda (patch) | |
| tree | 5bfd5aa5969b7dc192711e76591d6588e4f9b66d /arch/arm/mach-tegra/fuse.h | |
| parent | 198ce6b3b5ce5e48667bfb624b966f1e3842aa4e (diff) | |
ARM: tegra: clock: Set speedo_id according to actual fused SKU
- Read SKU_INFO fuse to get A02 SKU info
- Update CPU DVFS to use actual SKU info obtained
- Enable main table for EDP capping and thermal throttling
Original-Change-Id: I7ff3b06476998d77cc3f7a4fc03fb72e26b570db
Reviewed-on: http://git-master/r/32084
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
Rebase-Id: Re91f616032d8045ea2c28822e40f815f3e449931
Diffstat (limited to 'arch/arm/mach-tegra/fuse.h')
| -rw-r--r-- | arch/arm/mach-tegra/fuse.h | 19 |
1 files changed, 15 insertions, 4 deletions
diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h index ed2a2f995545..367308b21098 100644 --- a/arch/arm/mach-tegra/fuse.h +++ b/arch/arm/mach-tegra/fuse.h @@ -44,13 +44,24 @@ extern struct tegra_id tegra_id; unsigned long long tegra_chip_uid(void); unsigned int tegra_spare_fuse(int bit); int tegra_sku_id(void); -int tegra_cpu_process_id(void); -int tegra_core_process_id(void); -int tegra_soc_speedo_id(void); void tegra_init_fuse(void); -void tegra_init_speedo_data(void); u32 tegra_fuse_readl(unsigned long offset); void tegra_fuse_writel(u32 value, unsigned long offset); enum tegra_revision tegra_get_revision(void); const char *tegra_get_revision_name(void); +#ifndef CONFIG_TEGRA_FPGA_PLATFORM + +int tegra_cpu_process_id(void); +int tegra_core_process_id(void); +int tegra_soc_speedo_id(void); +void tegra_init_speedo_data(void); + +#else // CONFIG_TEGRA_FPGA_PLATFORM + +static inline int tegra_cpu_process_id(void) { return 0; } +static inline int tegra_core_process_id(void) { return 0; } +static inline int tegra_soc_speedo_id(void) { return 0; } +static inline void tegra_init_speedo_data(void) { } + +#endif// CONFIG_TEGRA_FPGA_PLATFORM |