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authorChris Fries <C.Fries@motorola.com>2010-11-11 17:39:06 -0600
committerDan Willemsen <dwillemsen@nvidia.com>2011-11-30 21:36:42 -0800
commitae9d0349aa9c45cb8779486f3d5fbface8c05f8b (patch)
tree3df90fa736e0106a90f8a9eb9ace3174f70bfc4c /arch/arm/mach-tegra/include/mach/dma.h
parent93b34bc619f44ea10e0ec63046e0c77f11cfa9d3 (diff)
[ARM] tegra: dma: Single buffered continuous DMA
- Added "single buffer continuous DMA" mode in addition to the "double buffer continuous DMA" mode that is already implemented - Changed the queuing of next buffer to be more flexible for continuous DMA. It can now get in-flight right after a transfer starts, or whenever the client enqueues a buffer. Signed-off-by: Iliyan Malchev <malchev@google.com>
Diffstat (limited to 'arch/arm/mach-tegra/include/mach/dma.h')
-rw-r--r--arch/arm/mach-tegra/include/mach/dma.h6
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/include/mach/dma.h b/arch/arm/mach-tegra/include/mach/dma.h
index 243050693eec..f9b09cbd8166 100644
--- a/arch/arm/mach-tegra/include/mach/dma.h
+++ b/arch/arm/mach-tegra/include/mach/dma.h
@@ -61,7 +61,9 @@ struct tegra_dma_channel;
enum tegra_dma_mode {
TEGRA_DMA_SHARED = 1,
TEGRA_DMA_MODE_CONTINUOUS = 2,
- TEGRA_DMA_MODE_ONESHOT = 4,
+ TEGRA_DMA_MODE_CONTINUOUS_DOUBLE = TEGRA_DMA_MODE_CONTINUOUS,
+ TEGRA_DMA_MODE_CONTINUOUS_SINGLE = 4,
+ TEGRA_DMA_MODE_ONESHOT = 8,
};
enum tegra_dma_req_error {
@@ -146,9 +148,11 @@ void tegra_dma_flush(struct tegra_dma_channel *ch);
bool tegra_dma_is_req_inflight(struct tegra_dma_channel *ch,
struct tegra_dma_req *req);
bool tegra_dma_is_empty(struct tegra_dma_channel *ch);
+bool tegra_dma_is_stopped(struct tegra_dma_channel *ch);
struct tegra_dma_channel *tegra_dma_allocate_channel(int mode);
void tegra_dma_free_channel(struct tegra_dma_channel *ch);
+int tegra_dma_cancel(struct tegra_dma_channel *ch);
int __init tegra_dma_init(void);