diff options
| author | Pavan Kunapuli <pkunapuli@nvidia.com> | 2011-09-02 15:32:00 +0530 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:48:48 -0800 |
| commit | 88d9501b29bfa2df6486fccf15c8dab8a33e72b9 (patch) | |
| tree | af671194c55d2d5c870c7fda1db96d7eda8b9efe /arch/arm/mach-tegra/pinmux.c | |
| parent | 3c98da80dd14ac10cd8effd7a1c60afb69825a91 (diff) | |
ARM: Tegra: Pinmux: Fix drive strength configuration
In T30, different pad ctrl group registers have
different pull up and pull down drive strength field
offsets and maximum values. Modified drive_strength
structure to be able to pass the offsets and masks of
each group to ensure that drive strengths are properly
configured.
Bug 870369
Original-Change-Id: Ib1872417542236c95c3b41a1ad860ef8418f5704
Reviewed-on: http://git-master/r/49872
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R4889bbb8bc0e5fef57d98bc68cd0116a9be3fdbd
Diffstat (limited to 'arch/arm/mach-tegra/pinmux.c')
| -rw-r--r-- | arch/arm/mach-tegra/pinmux.c | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/arch/arm/mach-tegra/pinmux.c b/arch/arm/mach-tegra/pinmux.c index b6742f431715..f16706d6bba4 100644 --- a/arch/arm/mach-tegra/pinmux.c +++ b/arch/arm/mach-tegra/pinmux.c @@ -709,6 +709,7 @@ static int tegra_drive_pinmux_set_pull_down(enum tegra_drive_pingroup pg, { unsigned long flags; u32 reg; + if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP) return -ERANGE; @@ -718,8 +719,9 @@ static int tegra_drive_pinmux_set_pull_down(enum tegra_drive_pingroup pg, spin_lock_irqsave(&mux_lock, flags); reg = pg_readl(drive_pingroups[pg].reg); - reg &= ~(0x1f << 12); - reg |= pull_down << 12; + reg &= ~(drive_pingroups[pg].drvdown_mask << + drive_pingroups[pg].drvdown_offset); + reg |= pull_down << drive_pingroups[pg].drvdown_offset; pg_writel(reg, drive_pingroups[pg].reg); spin_unlock_irqrestore(&mux_lock, flags); @@ -732,6 +734,7 @@ static int tegra_drive_pinmux_set_pull_up(enum tegra_drive_pingroup pg, { unsigned long flags; u32 reg; + if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP) return -ERANGE; @@ -741,8 +744,9 @@ static int tegra_drive_pinmux_set_pull_up(enum tegra_drive_pingroup pg, spin_lock_irqsave(&mux_lock, flags); reg = pg_readl(drive_pingroups[pg].reg); - reg &= ~(0x1f << 20); - reg |= pull_up << 20; + reg &= ~(drive_pingroups[pg].drvup_mask << + drive_pingroups[pg].drvup_offset); + reg |= pull_up << drive_pingroups[pg].drvup_offset; pg_writel(reg, drive_pingroups[pg].reg); spin_unlock_irqrestore(&mux_lock, flags); |