diff options
| author | Joshua Cha <joshuac@nvidia.com> | 2011-11-14 10:37:31 +0900 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:50:01 -0800 |
| commit | 98277cf86e97687a75f5e6c28ed00542075819ea (patch) | |
| tree | 8d110a21029955c9055820efadd2857fbc7ca2c6 /arch/arm/mach-tegra/pm.c | |
| parent | f4fbf45d89ba27da05f37b35d0a67308df2a2a22 (diff) | |
ARM: tegra: power: add combined power req processing
For platforms where the core & CPU power requests are combined
as a single request to the PMU, we need separate processing to
enable its suspend/resume operation.
Bug 862504
Change-Id: If66282a7b069d35568147e2d64f14371e1692bfd
Reviewed-on: http://git-master/r/64011
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: R21b966a438be03b11b80ce7deb70e3036b80dab2
Diffstat (limited to 'arch/arm/mach-tegra/pm.c')
| -rw-r--r-- | arch/arm/mach-tegra/pm.c | 31 |
1 files changed, 28 insertions, 3 deletions
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index f43954d5a9d5..ae11ceb841e5 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -533,7 +533,10 @@ unsigned int tegra_idle_lp2_last(unsigned int sleep_time, unsigned int flags) /* Only the last cpu down does the final suspend steps */ mode = readl(pmc + PMC_CTRL); mode |= TEGRA_POWER_CPU_PWRREQ_OE; - mode |= TEGRA_POWER_PWRREQ_OE; + if (pdata->combined_req) + mode &= ~TEGRA_POWER_PWRREQ_OE; + else + mode |= TEGRA_POWER_PWRREQ_OE; mode &= ~TEGRA_POWER_EFFECT_LP0; pmc_32kwritel(mode, PMC_CTRL); mode |= flags; @@ -660,11 +663,19 @@ static void tegra_pm_set(enum tegra_suspend_mode mode) reg = readl(pmc + PMC_CTRL); reg |= TEGRA_POWER_CPU_PWRREQ_OE; - reg |= TEGRA_POWER_PWRREQ_OE; + if (pdata->combined_req) + reg &= ~TEGRA_POWER_PWRREQ_OE; + else + reg |= TEGRA_POWER_PWRREQ_OE; reg &= ~TEGRA_POWER_EFFECT_LP0; switch (mode) { case TEGRA_SUSPEND_LP0: + if (pdata->combined_req) { + reg |= TEGRA_POWER_PWRREQ_OE; + reg &= ~TEGRA_POWER_CPU_PWRREQ_OE; + } + /* * LP0 boots through the AVP, which then resumes the AVP to * the address in scratch 39, and the cpu to the address in @@ -811,6 +822,19 @@ int tegra_suspend_dram(enum tegra_suspend_mode mode, unsigned int flags) restore_cpu_complex(flags); + /* for platforms where the core & CPU power requests are + * combined as a single request to the PMU, transition out + * of LP0 state by temporarily enabling both requests + */ + if (mode == TEGRA_SUSPEND_LP0 && pdata->combined_req) { + u32 reg; + reg = readl(pmc + PMC_CTRL); + reg |= TEGRA_POWER_CPU_PWRREQ_OE; + pmc_32kwritel(reg, PMC_CTRL); + reg &= ~TEGRA_POWER_PWRREQ_OE; + pmc_32kwritel(reg, PMC_CTRL); + } + cpu_complex_pm_exit(); cpu_pm_exit(); @@ -1050,7 +1074,8 @@ out: /* now enable requests */ reg |= TEGRA_POWER_SYSCLK_OE; - reg |= TEGRA_POWER_PWRREQ_OE; + if (!pdata->combined_req) + reg |= TEGRA_POWER_PWRREQ_OE; pmc_32kwritel(reg, PMC_CTRL); if (pdata->suspend_mode == TEGRA_SUSPEND_LP0) |