diff options
| author | Bo Yan <byan@nvidia.com> | 2012-05-18 19:55:18 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 12:11:27 -0700 |
| commit | 04d92858c7aefe33a414a3790da0c724ed17dddc (patch) | |
| tree | 525c083c50f8a38251d4f4f6dcb3d4f065a73c45 /arch/arm/mach-tegra/pm.h | |
| parent | 175688b060b343288a9e4dd93e142e695d0aa6d9 (diff) | |
ARM: tegra: Clean up flow controller CSR macros
Group flow controller macros for CSR register in one place in sleep.h
Also strip "CPU" out of macro names because the corresponding COP CSR
register has only one field INTR_FLAG which is at bit 15, same as CPU
CSR, so there is no confusion here.
Change-Id: Ib3dea0bd3e9051d1e7b9048abc4afde5ddc8bab5
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/103478
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Jin Qian <jqian@nvidia.com>
Rebase-Id: R63c198f17e573818b8d44482c46cb61516bf1267
Diffstat (limited to 'arch/arm/mach-tegra/pm.h')
| -rw-r--r-- | arch/arm/mach-tegra/pm.h | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h index a5b7ce7ef9b2..a40d384d16eb 100644 --- a/arch/arm/mach-tegra/pm.h +++ b/arch/arm/mach-tegra/pm.h @@ -84,13 +84,6 @@ int tegra_suspend_dram(enum tegra_suspend_mode mode, unsigned int flags); #define FLOW_CTRL_CLUSTER_CONTROL \ (IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + 0x2c) -#define FLOW_CTRL_CPU_CSR_ENABLE_EXT_CRAIL (1<<13) -#define FLOW_CTRL_CPU_CSR_ENABLE_EXT_NCPU (1<<12) -#define FLOW_CTRL_CPU_CSR_ENABLE_EXT_MASK ( \ - FLOW_CTRL_CPU_CSR_ENABLE_EXT_NCPU | \ - FLOW_CTRL_CPU_CSR_ENABLE_EXT_CRAIL ) -#define FLOW_CTRL_CPU_CSR_IMMEDIATE_WAKE (1<<3) -#define FLOW_CTRL_CPU_CSR_SWITCH_CLUSTER (1<<2) #define FLOW_CTRL_CPU_PWR_CSR \ (IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + 0x38) |