diff options
| author | Alex Frid <afrid@nvidia.com> | 2013-08-15 19:03:07 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 13:41:56 -0700 |
| commit | 3b6ed5e6779109c1c53cd8c856411d407497ba9e (patch) | |
| tree | 08f7ab7faca91006c1f930f1319e38698f4a72af /arch/arm/mach-tegra/pm.h | |
| parent | 7fce58a4fee59eef6837480884602a18e25abae1 (diff) | |
ARM: tegra: power: Support CPU rail early startup
Added an option for cluster switch procedure to turn CPU rail ON
via direct access to PMC registers before disabling interrupts,
and then continue scheduler execution while the rail is ramping up.
RAM repair is executed in s/w as well after rail ramp is done. Only
non-CPU partition is power-gated/un-gated by flow controller in the
atomic section. However, rail ramp in this case is serialized with
CPU save context. Hence the trade-off: early startup option reduces
interrupt disabled time during cluster switch, but increases overall
cluster switch time.
Bug 1351735
Change-Id: I5ff9afb2aa6b27b9aa4b2318ee2740dee4908e2f
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/262864
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/pm.h')
| -rw-r--r-- | arch/arm/mach-tegra/pm.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h index a04be5620f3a..88332a002d96 100644 --- a/arch/arm/mach-tegra/pm.h +++ b/arch/arm/mach-tegra/pm.h @@ -86,6 +86,7 @@ struct tegra_suspend_platform_data { unsigned long min_residency_ncpu_slow; unsigned long min_residency_ncpu_fast; unsigned long min_residency_crail; + bool crail_up_early; #endif unsigned long min_residency_mc_clk; bool usb_vbus_internal_wake; /* support for internal vbus wake */ @@ -106,7 +107,12 @@ unsigned long tegra_mc_clk_stop_min_residency(void); unsigned long tegra_min_residency_vmin_fmin(void); unsigned long tegra_min_residency_ncpu(void); unsigned long tegra_min_residency_crail(void); +bool tegra_crail_can_start_early(void); +#else +static inline bool tegra_crail_can_start_early(void) +{ return false; } #endif +void tegra_limit_cpu_power_timers(unsigned long us_on, unsigned long us_off); void tegra_clear_cpu_in_pd(int cpu); bool tegra_set_cpu_in_pd(int cpu); @@ -135,6 +141,8 @@ unsigned long tegra_lp1bb_emc_min_rate_get(void); #define FLOW_CTRL_RAM_REPAIR \ (IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + 0x40) #define FLOW_CTRL_RAM_REPAIR_BYPASS_EN (1<<2) +#define FLOW_CTRL_RAM_REPAIR_STS (1<<1) +#define FLOW_CTRL_RAM_REPAIR_REQ (1<<0) #define FUSE_SKU_DIRECT_CONFIG \ (IO_ADDRESS(TEGRA_FUSE_BASE) + 0x1F4) |