diff options
| author | Bo Yan <byan@nvidia.com> | 2012-10-13 14:09:52 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 12:40:18 -0700 |
| commit | 4fd53bed2e8d45b72e4ba368123c4d9e4ba3c311 (patch) | |
| tree | 0b71905d09f0924b2aa11342ffb3ac2e98128a3a /arch/arm/mach-tegra/pm.h | |
| parent | ad85f86ab049b4816a4bf5f3d0c3a110e612d109 (diff) | |
ARM: tegra11x: CPUID virtualization support
This is the first patch to support CPUID virtualization. The goal is
to treat all CPUs as equal in software. In current implementation,
CPU0 is the anchor CPU, which must be the first one brought up, and
the last one taken down. This patch removes that restriction.
the cluster switch still has to start from CPU0 with this patch.
This can not coexist with secure OS
Reviewed-on: http://git-master/r/144610
(cherry picked from commit d32fba4be39e3f9a95ef5ab44d0c64dc6d2808a3)
Change-Id: Ib7fcaae751d17fee839a4f228f5ef5c3ee2390c2
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/159486
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
Rebase-Id: R09e29d45acf92b3ad2d909d5438c3375aa85e7dd
Diffstat (limited to 'arch/arm/mach-tegra/pm.h')
| -rw-r--r-- | arch/arm/mach-tegra/pm.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h index 0f962c6370e8..9754ce01eef7 100644 --- a/arch/arm/mach-tegra/pm.h +++ b/arch/arm/mach-tegra/pm.h @@ -101,6 +101,9 @@ int tegra_suspend_dram(enum tegra_suspend_mode mode, unsigned int flags); (IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + 0x38) #define FLOW_CTRL_CPU_PWR_CSR_RAIL_ENABLE 1 +#define FLOW_CTRL_MPID \ + (IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + 0x3c) + #define FLOW_CTRL_RAM_REPAIR \ (IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + 0x40) #define FLOW_CTRL_RAM_REPAIR_BYPASS_EN (1<<2) |