diff options
| author | Eric Yuen <eyuen@nvidia.com> | 2014-07-08 10:34:33 +0000 |
|---|---|---|
| committer | Winnie Hsu <whsu@nvidia.com> | 2014-10-10 15:31:43 -0700 |
| commit | 36a8e8ba4538d17acaac60ffca6835cf21f33709 (patch) | |
| tree | a9f83f7a0a34c5edf3569c676d93f9c6234d7fe9 /arch/arm/mach-tegra/powergate.c | |
| parent | bc4bd19dd6e9de8518a784753d7b69224be0b9f6 (diff) | |
arm: tegra3: PCIe Clock and Reset Conform to Specification
PCIe Reset line must be asserted for at least 100us after clock is enabled.
PEX 2 Controller Register fix, offsets are not at constant intervals.
Bug 1521306
Reviewed-on: http://git-master/r/225399
(cherry picked from commit df0760bf515236bed2e87e590509642ab72a01b5)
Change-Id: I7b44ea51e7e02f2bca93cfc75ed85e01ab91fe03
Signed-off-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-on: http://git-master/r/435598
Reviewed-by: Jay Agarwal <jagarwal@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Eric Brower <ebrower@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/powergate.c')
0 files changed, 0 insertions, 0 deletions