diff options
| author | Prashant Gaikwad <pgaikwad@nvidia.com> | 2013-05-31 14:45:32 +0530 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 13:16:46 -0700 |
| commit | 5fd27c0a74265731edb771ed91680a658dc9f7bf (patch) | |
| tree | b939822e1cc260d79e9eecfd9631c19b186e79ba /arch/arm/mach-tegra/sleep-t30.S | |
| parent | 193b5d71aaec97aa22a9c114fb0a1c2742c422e8 (diff) | |
arm: tegra: save and restore EMC_REFRESH value
After exit from LP1/LP0 EMC_REFRESH was restored to 1 which
is incorrect from timing perspective. It was working fine
with system suspend state since later frequency switch will
restore it to correct value. But for LP1 in idle it regressed
power on DDR power rails since DRAM dynamic self refresh will
not work.
Bug 1294838
Change-Id: I0aa9a7ef74f28a97cd1603179f2362d223b10c76
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/234474
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/sleep-t30.S')
| -rw-r--r-- | arch/arm/mach-tegra/sleep-t30.S | 37 |
1 files changed, 22 insertions, 15 deletions
diff --git a/arch/arm/mach-tegra/sleep-t30.S b/arch/arm/mach-tegra/sleep-t30.S index c12103d90ec3..4342bcac1432 100644 --- a/arch/arm/mach-tegra/sleep-t30.S +++ b/arch/arm/mach-tegra/sleep-t30.S @@ -463,10 +463,10 @@ ENTRY(tegra3_lp1_reset) add r5, pc, #tegra11_sdram_pad_save-(.+8) @ r5 --> saved data #endif - ldr r4, [r5, #0x18] + ldr r4, [r5, #0x1c] str r4, [r0, #CLK_RESET_CLK_SOURCE_MSELECT] - ldr r4, [r5, #0x1C] + ldr r4, [r5, #0x20] str r4, [r0, #CLK_RESET_SCLK_BURST] #if defined(CONFIG_ARCH_TEGRA_3x_SOC) mov32 r4, ((1<<28) | (8)) @ burst policy is PLLX @@ -572,7 +572,7 @@ emc_exit_selfrefresh: add r5, pc, #tegra11_sdram_pad_save-(.+8) @ r5 --> saved data #endif - ldr r1, [r5, #0x14] @ PMC_IO_DPD_STATUS + ldr r1, [r5, #0x18] @ PMC_IO_DPD_STATUS mvn r1, r1 bic r1, r1, #(0x1<<31) orr r1, r1, #(0x1<<30) @@ -619,6 +619,7 @@ emc_wait_audo_cal_onetime: str r1, [r0, #EMC_NOP] str r1, [r0, #EMC_NOP] #endif + ldr r1, [r5, #0x14] str r1, [r0, #EMC_REFRESH] emc_device_mask r1, r0 @@ -689,7 +690,7 @@ zcal_done: mov32 r1, TEGRA_EMC1_BASE cmp r0, r1 movne r0, r1 - addne r5, r5, #0x20 + addne r5, r5, #0x24 bne exit_self_refresh #endif @@ -720,6 +721,7 @@ tegra3_sdram_pad_save: .word 0 .word 0 .word 0 + .word 0 tegra3_sdram_pad_address: .word TEGRA_EMC_BASE + EMC_CFG @0x0 @@ -727,9 +729,10 @@ tegra3_sdram_pad_address: .word TEGRA_EMC_BASE + EMC_AUTO_CAL_INTERVAL @0x8 .word TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL @0xc .word TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL2 @0x10 - .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14 - .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18 - .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c + .word TEGRA_EMC_BASE + EMC_REFRESH @0x14 + .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x18 + .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x1c + .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x20 #endif #if defined(CONFIG_ARCH_TEGRA_11x_SOC) .align L1_CACHE_SHIFT @@ -748,6 +751,8 @@ tegra11_sdram_pad_save: .word 0 .word 0 .word 0 + .word 0 + .word 0 tegra11_sdram_pad_address: .word TEGRA_EMC0_BASE + EMC_CFG @0x0 @@ -755,14 +760,16 @@ tegra11_sdram_pad_address: .word TEGRA_EMC0_BASE + EMC_AUTO_CAL_INTERVAL @0x8 .word TEGRA_EMC0_BASE + EMC_XM2VTTGENPADCTRL @0xc .word TEGRA_EMC0_BASE + EMC_XM2VTTGENPADCTRL2 @0x10 - .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14 - .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18 - .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c - .word TEGRA_EMC1_BASE + EMC_CFG @0x20 - .word TEGRA_EMC1_BASE + EMC_ZCAL_INTERVAL @0x24 - .word TEGRA_EMC1_BASE + EMC_AUTO_CAL_INTERVAL @0x28 - .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL @0x2c - .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2 @0x30 + .word TEGRA_EMC0_BASE + EMC_REFRESH @0x14 + .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x18 + .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x1c + .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x20 + .word TEGRA_EMC1_BASE + EMC_CFG @0x24 + .word TEGRA_EMC1_BASE + EMC_ZCAL_INTERVAL @0x28 + .word TEGRA_EMC1_BASE + EMC_AUTO_CAL_INTERVAL @0x2c + .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL @0x30 + .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2 @0x34 + .word TEGRA_EMC1_BASE + EMC_REFRESH @0x38 #endif #ifdef CONFIG_TEGRA_LP1_LOW_COREVOLTAGE |