diff options
| author | Alex Frid <afrid@nvidia.com> | 2013-06-15 19:11:15 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-16 17:41:27 -0700 |
| commit | 70e4e08132d8cde78f270b7c47c9c682d5e2cb39 (patch) | |
| tree | 0a3db044e7315ff7d7c3fe9dea3b76d2a3da1287 /arch/arm/mach-tegra/sleep-t30.S | |
| parent | c815d2cf6d6c91fc063a2c23dc62b17c07c312a3 (diff) | |
ARM: tegra: power: Disable CL-DVFS clock on LP1 entry
Disabled CL-DVFS logic clock on LP1 entry, and re-enabled it during
resume. If running DFLL is in open loop in LP1, and there is no need
to clock closed loop logic.
Change-Id: I097aa431d99cd24d1dd6a409ad37faecf8f579dd
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/239134
(cherry picked from commit 8b56a79525817fab6e4bc7a6d905f6544d791116)
Reviewed-on: http://git-master/r/240863
(cherry picked from commit adbe3ecbb0d81a8a5eaf548dc209cabdd2f58a51)
Reviewed-on: http://git-master/r/271888
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/sleep-t30.S')
| -rw-r--r-- | arch/arm/mach-tegra/sleep-t30.S | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/sleep-t30.S b/arch/arm/mach-tegra/sleep-t30.S index 2dde9e9309cb..a653092fa97b 100644 --- a/arch/arm/mach-tegra/sleep-t30.S +++ b/arch/arm/mach-tegra/sleep-t30.S @@ -108,6 +108,10 @@ #define CLK_RESET_CLK_ENB_H_CLR 0x32c #define CLK_RESET_CLK_RST_DEV_H_SET 0x308 #define CLK_RESET_CLK_RST_DEV_H_CLR 0x30c +#if !defined(CONFIG_ARCH_TEGRA_3x_SOC) +#define CLK_RESET_CLK_ENB_W_SET 0x448 +#define CLK_RESET_CLK_ENB_W_CLR 0x44c +#endif #define I2C_CNFG 0x0 #define I2C_ADDR0 0x4 @@ -462,6 +466,12 @@ resume_lp1: add r1, r1, #LOCK_DELAY wait_until r1, r7, r3 +#if !defined(CONFIG_ARCH_TEGRA_3x_SOC) + /* re-enable cl_dvfs logic clock (if dfll running, it's in open loop) */ + mov r4, #(1 << 27) + str r4, [r0, #CLK_RESET_CLK_ENB_W_SET] +#endif + #if defined(CONFIG_ARCH_TEGRA_3x_SOC) || \ defined(CONFIG_ARCH_TEGRA_14x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC) add r5, pc, #tegra3_sdram_pad_save-(.+8) @ r5 --> saved data @@ -1078,6 +1088,11 @@ lp1_volt_skip: orr r0, r0, #MSELECT_CLKM str r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT] +#if !defined(CONFIG_ARCH_TEGRA_3x_SOC) + /* disable cl_dvfs logic clock (if dfll running, it's in open loop) */ + mov r0, #(1 << 27) + str r0, [r5, #CLK_RESET_CLK_ENB_W_CLR] +#endif /* 2 us delay between changing sclk and disabling PLLs */ wait_for_us r1, r7, r9 add r1, r1, #2 |