diff options
| author | Bo Yan <byan@nvidia.com> | 2013-11-06 11:34:03 -0800 |
|---|---|---|
| committer | Bo Yan <byan@nvidia.com> | 2013-11-07 08:31:54 -0800 |
| commit | 7c74b5a27bcfba034d7112440b6c6a4a3ea66b56 (patch) | |
| tree | 01aa3d9630dd65092dd252f5c27a27753db72c96 /arch/arm/mach-tegra/sleep-t30.S | |
| parent | ee1cf49544f806a9c066604af93332225c700ee9 (diff) | |
arm: tegra: bypass PllP during LP1 suspend
RAM repair requires PllP, so it shouldn't be disabled. To save
power, instead of keeping it running at 408Mhz, enable bypass
mode, so RAM repair logic can be clocked by oscillator. This
is done when LP1 entry is from fast cluster only.
In addition, change PLLP_OUT0_RATIO to 0 so the reshift clock
is not being further divided down, change it back to default
value after PllP is enabled and bypass is disabled.
This change is copied from http://git-master/r/310133 . The
cherry-pick doesn't work since the original file was deleted.
bug 1373419
Change-Id: I77a3a62515c8513ca12854483c36da6937b1f9e3
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/327266
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/sleep-t30.S')
| -rw-r--r-- | arch/arm/mach-tegra/sleep-t30.S | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/sleep-t30.S b/arch/arm/mach-tegra/sleep-t30.S index ace80b73525d..1153f7c6b38f 100644 --- a/arch/arm/mach-tegra/sleep-t30.S +++ b/arch/arm/mach-tegra/sleep-t30.S @@ -84,6 +84,10 @@ #define CLK_RESET_PLLA_BASE 0xb0 #define CLK_RESET_PLLX_BASE 0xe0 +#define CLK_RESET_PLLP_RESHIFT 0x528 +#define CLK_RESET_PLLP_RESHIFT_DEFAULT 0x3b +#define CLK_RESET_PLLP_RESHIFT_ENABLE 0x3 + #define CLK_RESET_PLLC_MISC 0x8c #define CLK_RESET_PLLM_MISC 0x9c #define CLK_RESET_PLLP_MISC 0xac @@ -121,6 +125,8 @@ #define MSELECT_CLKM (0x3 << 30) +#define FLOW_CONTROL_CLUSTER_CONTROL 0x2c + #define TEGRA_RTC_MSEC 0x10 #if USE_PLL_LOCK_BITS @@ -491,6 +497,15 @@ resume_lp1: pll_locked r1, r0, CLK_RESET_PLLC_BASE pll_locked r1, r0, CLK_RESET_PLLX_BASE +#if !defined(CONFIG_ARCH_TEGRA_3x_SOC) + ldr r1, [r0, #CLK_RESET_PLLP_BASE] + bic r1, r1, #(1<<31) /* disable PllP bypass */ + str r1, [r0, #CLK_RESET_PLLP_BASE] + + mov r1, #CLK_RESET_PLLP_RESHIFT_DEFAULT + str r1, [r0, #CLK_RESET_PLLP_RESHIFT] +#endif + mov32 r7, TEGRA_TMRUS_BASE ldr r1, [r7] add r1, r1, #LOCK_DELAY @@ -1192,9 +1207,18 @@ lp1bb_emc_source_check: b powerdown_pll_cx @ if not, turn off pll-c/pll-x #endif powerdown_pll_pacx: + ldr r0, [r6, #FLOW_CONTROL_CLUSTER_CONTROL] + tst r0, #1 ldr r0, [r5, #CLK_RESET_PLLP_BASE] bic r0, r0, #(1<<30) +#if !defined(CONFIG_ARCH_TEGRA_3x_SOC) + orreq r0, r0, #(1<<31) @ enable PllP bypass on fast +#endif str r0, [r5, #CLK_RESET_PLLP_BASE] +#if !defined(CONFIG_ARCH_TEGRA_3x_SOC) + mov r0, #CLK_RESET_PLLP_RESHIFT_ENABLE + str r0, [r5, #CLK_RESET_PLLP_RESHIFT] +#endif ldr r0, [r5, #CLK_RESET_PLLA_BASE] bic r0, r0, #(1<<30) str r0, [r5, #CLK_RESET_PLLA_BASE] |