diff options
| author | Prashant Malani <pmalani@nvidia.com> | 2013-01-31 18:43:48 -0800 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 12:59:44 -0700 |
| commit | 7c8651060d5a3dc309dc23b8d1314cc2df1e7b13 (patch) | |
| tree | 005884017e2498552bf175b89d4522cb54196cf8 /arch/arm/mach-tegra/sleep-t30.S | |
| parent | 82de4878d2418bc43507f6f12fc80fe7f93d7713 (diff) | |
ARM: tegra14x: Add POR_PAD_CTRL programming
Need to program PMC_POR_PAD_CTRL register during
LP0 entry as required by H/W
Bug 978296
Change-Id: Id7b8b0df9b5782af8da7c2581a32717e94776e16
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/196235
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/sleep-t30.S')
| -rw-r--r-- | arch/arm/mach-tegra/sleep-t30.S | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/sleep-t30.S b/arch/arm/mach-tegra/sleep-t30.S index 9fda53d11215..517b7725aa7d 100644 --- a/arch/arm/mach-tegra/sleep-t30.S +++ b/arch/arm/mach-tegra/sleep-t30.S @@ -63,6 +63,7 @@ #define PMC_IO_DPD_REQ 0x1b8 #define PMC_IO_DPD_STATUS 0x1bc #define PMC_SCRATCH1_ECO 0x264 +#define PMC_POR_DPD_CTRL 0x264 #define FLOW_IPC_STS 0x500 #define FLOW_IPC_STS_AP2BB_MSC_STS_0 (1 << 4) @@ -883,6 +884,12 @@ tegra3_cpu_clk32k: str r1, [r4, #PMC_SCRATCH1_ECO] #endif +#if defined(CONFIG_ARCH_TEGRA_14x_SOC) + ldr r1, [r4, #PMC_POR_DPD_CTRL] + orr r1, r1, #0x47 + str r1, [r4, #PMC_POR_DPD_CTRL] +#endif + mov pc, lr lp1_clocks_prepare: |