diff options
| author | Nitin Sehgal <nsehgal@nvidia.com> | 2014-02-06 12:22:45 +0530 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2014-02-09 21:54:20 -0800 |
| commit | 7f93a0dddf39f372c064f772f9af6903e91aaacf (patch) | |
| tree | 771484fe44d5857a58ca2b20c3dde9820584737e /arch/arm/mach-tegra/sleep-t30.S | |
| parent | 76fdf095ea7881e7f62621d6c6baabc4e50e660f (diff) | |
ARM: tegra: trustzone: Single kernel to work in both secure and non-secure mode.
- Remove CONFIG_TEGRA_USE_SECURE_KERNEL config option
- Use DBGDSCR.NS bit to dynamically get secure/non-secure mode
- Replace ifdefs with dynamic code.
- Keep CONFIG_TRUSTED_LITTLE_KERNEL to enable secure os
bug 1411345
Change-Id: I75ddfed7a35fcb30e2772bb43057ae022bcf09b3
Signed-off-by: Nitin Sehgal <nsehgal@nvidia.com>
Reviewed-on: http://git-master/r/353155
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Tested-by: Varun Wadekar <vwadekar@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/sleep-t30.S')
| -rw-r--r-- | arch/arm/mach-tegra/sleep-t30.S | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/arch/arm/mach-tegra/sleep-t30.S b/arch/arm/mach-tegra/sleep-t30.S index 98e836ca8f3a..e64cad95d2f3 100644 --- a/arch/arm/mach-tegra/sleep-t30.S +++ b/arch/arm/mach-tegra/sleep-t30.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -456,7 +456,10 @@ enable_mc: resume_lp1: mov32 r0, TEGRA_CLK_RESET_BASE -#if !defined(CONFIG_TEGRA_USE_SECURE_KERNEL) + bl is_secure_mode + cmp r0, #1 + mov32 r0, TEGRA_CLK_RESET_BASE + bne 1f @Skip if non-secure mode /* secure code handles 32KHz to CLKM/OSC clock switch */ mov r1, #(1<<28) str r1, [r0, #CLK_RESET_SCLK_BURST] @@ -464,8 +467,7 @@ resume_lp1: mov r1, #0 str r1, [r0, #CLK_RESET_SCLK_DIVIDER] str r1, [r0, #CLK_RESET_CCLK_DIVIDER] -#endif - +1: #if defined(CONFIG_ARCH_TEGRA_3x_SOC) /* enable PLLM via PMC */ mov32 r2, TEGRA_PMC_BASE |