diff options
| author | Prashant Malani <pmalani@nvidia.com> | 2013-01-30 15:04:19 -0800 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 12:59:13 -0700 |
| commit | aa99d728684b7bae64d087c0524bf717b11c5742 (patch) | |
| tree | 7d3f6dd7f0d7e1467e89e3418e7c5bf77ba94b64 /arch/arm/mach-tegra/sleep-t30.S | |
| parent | 16d1ba89cf405215a69e8a8607dcc34cc16c6412 (diff) | |
ARM: tegra14x: Disable PLLP lock status bit
After LP0 entry, PLLP lock status bit, stored in
FLOW_IPC_STS register, should be cleared.
Bug 1160000
Change-Id: Ie14c5684e8b673dacdcd66f853aae5e9408f6373
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/195715
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/sleep-t30.S')
| -rw-r--r-- | arch/arm/mach-tegra/sleep-t30.S | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/sleep-t30.S b/arch/arm/mach-tegra/sleep-t30.S index aed80d4efdd4..d801d4903a90 100644 --- a/arch/arm/mach-tegra/sleep-t30.S +++ b/arch/arm/mach-tegra/sleep-t30.S @@ -64,6 +64,9 @@ #define PMC_IO_DPD_STATUS 0x1bc #define PMC_SCRATCH1_ECO 0x264 +#define FLOW_IPC_STS 0x500 +#define FLOW_IPC_STS_AP2BB_MSC_STS_0 (1 << 4) + #define CLK_RESET_CCLK_BURST 0x20 #define CLK_RESET_CCLK_DIVIDER 0x24 #define CLK_RESET_SCLK_BURST 0x28 @@ -747,6 +750,11 @@ tegra148_lp0_entry: orr r1, r1, #PMC_IPC_CLR_MEM_STS str r1, [r4, #PMC_IPC_CLR] + /* Clear FLOW_I2C_STS[AP2BB_MSC_STS[0]] */ + ldr r1, [r6, #FLOW_IPC_STS] + bic r1, #FLOW_IPC_STS_AP2BB_MSC_STS_0 + str r1, [r6, #FLOW_IPC_STS] + /* Check PMC_IPC_STS[mem_req] and PMC_IPC_STS[mem_req_soon] * once again. If both 0 then go to LP0 entry */ |