diff options
| author | Alex Frid <afrid@nvidia.com> | 2013-06-20 23:57:12 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 13:39:56 -0700 |
| commit | acc81cd52d91bbdfe584d428805c0561657658cf (patch) | |
| tree | 1cdcfb0f3be327cea177710958748f7a3eb64ddd /arch/arm/mach-tegra/sleep-t30.S | |
| parent | 886f0466ac973a476e28bc0d5c41c2ce5c9a5174 (diff) | |
ARM: tegra: clock: Restore CPU clock source after LP1
Restore CPU clock source after LP1 early - before CPU context (before
this commit CPU run on oscillator until clock resume syscore call).
Bug 1292094
Change-Id: Ida0d92f4744578e0fd6b32edacff109ae6bff42b
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/241176
(cherry picked from commit 5d7e97404d356ac6714dcf42a6e8361e72015375)
Signed-off-by: Alex Frid <afrid@nvidia.com>
Change-Id: Ic6322d8e0950f6f93aa719eebce8f76e444721ba
Reviewed-on: http://git-master/r/260242
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/sleep-t30.S')
| -rw-r--r-- | arch/arm/mach-tegra/sleep-t30.S | 29 |
1 files changed, 23 insertions, 6 deletions
diff --git a/arch/arm/mach-tegra/sleep-t30.S b/arch/arm/mach-tegra/sleep-t30.S index 92d4b2341210..2dde9e9309cb 100644 --- a/arch/arm/mach-tegra/sleep-t30.S +++ b/arch/arm/mach-tegra/sleep-t30.S @@ -73,6 +73,7 @@ #define FLOW_IPC_STS_AP2BB_MSC_STS_0 (1 << 4) #define CLK_RESET_CCLK_BURST 0x20 +#define CCLK_BURST_PLLX_DIV2_BYPASS_LP (1<<16) #define CLK_RESET_CCLK_DIVIDER 0x24 #define CLK_RESET_SCLK_BURST 0x28 #define CLK_RESET_SCLK_DIVIDER 0x2c @@ -477,6 +478,18 @@ defined(CONFIG_ARCH_TEGRA_14x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC) #if defined(CONFIG_ARCH_TEGRA_3x_SOC) mov32 r4, ((1<<28) | (8)) @ burst policy is PLLX str r4, [r0, #CLK_RESET_CCLK_BURST] +#else + /* first restore PLLX div2 state, 2us delay, then CPU clock source */ + ldr r4, [r5, #0x20] + tst r4, #CCLK_BURST_PLLX_DIV2_BYPASS_LP + ldr r1, [r0, #CLK_RESET_CCLK_BURST] + biceq r1, r1, #CCLK_BURST_PLLX_DIV2_BYPASS_LP + orrne r1, r1, #CCLK_BURST_PLLX_DIV2_BYPASS_LP + str r1, [r0, #CLK_RESET_CCLK_BURST] + ldr r1, [r7] + add r1, r1, #2 + wait_until r1, r7, r3 + str r4, [r0, #CLK_RESET_CCLK_BURST] #endif #ifdef CONFIG_TEGRA_LP1_LOW_COREVOLTAGE @@ -731,6 +744,7 @@ tegra3_sdram_pad_save: .word 0 .word 0 .word 0 + .word 0 tegra3_sdram_pad_address: .word TEGRA_EMC_BASE + EMC_CFG @0x0 @@ -742,6 +756,7 @@ tegra3_sdram_pad_address: .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x18 .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x1c .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x20 + .word TEGRA_CLK_RESET_BASE + CLK_RESET_CCLK_BURST @0x24 #endif #if defined(CONFIG_ARCH_TEGRA_11x_SOC) .align L1_CACHE_SHIFT @@ -762,6 +777,7 @@ tegra11_sdram_pad_save: .word 0 .word 0 .word 0 + .word 0 tegra11_sdram_pad_address: .word TEGRA_EMC0_BASE + EMC_CFG @0x0 @@ -773,12 +789,13 @@ tegra11_sdram_pad_address: .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x18 .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x1c .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x20 - .word TEGRA_EMC1_BASE + EMC_CFG @0x24 - .word TEGRA_EMC1_BASE + EMC_ZCAL_INTERVAL @0x28 - .word TEGRA_EMC1_BASE + EMC_AUTO_CAL_INTERVAL @0x2c - .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL @0x30 - .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2 @0x34 - .word TEGRA_EMC1_BASE + EMC_REFRESH @0x38 + .word TEGRA_CLK_RESET_BASE + CLK_RESET_CCLK_BURST @0x24 + .word TEGRA_EMC1_BASE + EMC_CFG @0x28 + .word TEGRA_EMC1_BASE + EMC_ZCAL_INTERVAL @0x2c + .word TEGRA_EMC1_BASE + EMC_AUTO_CAL_INTERVAL @0x30 + .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL @0x34 + .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2 @0x38 + .word TEGRA_EMC1_BASE + EMC_REFRESH @0x3c #endif #ifdef CONFIG_TEGRA_LP1_LOW_COREVOLTAGE |