diff options
| author | Prashant Malani <pmalani@nvidia.com> | 2013-05-30 13:57:51 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 13:16:24 -0700 |
| commit | c682066e3789e4523e42e5323fc16bce745e2213 (patch) | |
| tree | 252271ed76f48fd419ee941feffa00f3d7baf301 /arch/arm/mach-tegra/sleep-t30.S | |
| parent | a0bbc23abdb2a5283dfdbadd757f46c8ad8fbc22 (diff) | |
ARM: tegra14: pm: don't always shut pllp in LP1BB
If we are entering in LP1BB, and EMC is running
off of PLLP, we should refrain from switching it
off.
Bug 1295878
Change-Id: I5c87edc231fde529fd7d28f1d5574ebb74cf8427
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/234273
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vinayak Pane <vpane@nvidia.com>
Tested-by: Vinayak Pane <vpane@nvidia.com>
Reviewed-by: Herve Fache <hfache@nvidia.com>
Tested-by: Herve Fache <hfache@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/sleep-t30.S')
| -rw-r--r-- | arch/arm/mach-tegra/sleep-t30.S | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/sleep-t30.S b/arch/arm/mach-tegra/sleep-t30.S index 730fbbc3e22a..8042780ad15d 100644 --- a/arch/arm/mach-tegra/sleep-t30.S +++ b/arch/arm/mach-tegra/sleep-t30.S @@ -104,6 +104,11 @@ #define CLK_RESET_CLK_RST_DEV_H_SET 0x308 #define CLK_RESET_CLK_RST_DEV_H_CLR 0x30c +#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC 0x19c +#define CLK_SOURCE_EMC_MASK (0x3 << 29) +#define CLK_SOURCE_EMC_BIT_OFFSET 29 +#define CLK_SOURCE_EMC_PLLP_OUT0 2 + #define I2C_CNFG 0x0 #define I2C_ADDR0 0x4 #define I2C_DATA1 0xc @@ -1048,9 +1053,26 @@ powerdown_pll_pcx: tst r11, #TEGRA_POWER_LP1_AUDIO @ check if voice call is going on bne powerdown_pll_cx @ if yes, do not turn off pll-p/pll-a + +#if defined(CONFIG_ARCH_TEGRA_14x_SOC) + ldr r0, lp_enter_state + cmp r0, #PMC_LP_STATE_LP1BB + bne turn_off_pllp + + /* If LP1BB, check if EMC is on PLLP */ + ldr r0, [r5, #CLK_RST_CONTROLLER_CLK_SOURCE_EMC] + and r0, #CLK_SOURCE_EMC_MASK + mov r0, r0, lsr #CLK_SOURCE_EMC_BIT_OFFSET + cmp r0, #CLK_SOURCE_EMC_PLLP_OUT0 + beq skip_pllp_off + +turn_off_pllp: +#endif ldr r0, [r5, #CLK_RESET_PLLP_BASE] bic r0, r0, #(1<<30) str r0, [r5, #CLK_RESET_PLLP_BASE] + +skip_pllp_off: ldr r0, [r5, #CLK_RESET_PLLA_BASE] bic r0, r0, #(1<<30) str r0, [r5, #CLK_RESET_PLLA_BASE] |