diff options
| author | Prashant Malani <pmalani@nvidia.com> | 2013-04-04 00:50:55 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 13:07:22 -0700 |
| commit | d6e8e93965bb2c5920f93fdd6845ccb13849873d (patch) | |
| tree | efd1ffe809546ae850045edbd69886ba473f3fe4 /arch/arm/mach-tegra/sleep-t30.S | |
| parent | aa104dbbe5aab0a3769ba93c67823439c6277313 (diff) | |
ARM: tegra14: Improve LP1BB branch code
Once mem_req and mem_req_soon are checked,
we should immediately jump to lp1bb entry
routines and not change the PMC_IPC_STS
or FLOW_IPC_STS register, even they get
restored later.
Bug 1257433
Change-Id: I7dc3732bbfe3b60fd047dd0b783235d66f3816e4
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/216421
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/sleep-t30.S')
| -rw-r--r-- | arch/arm/mach-tegra/sleep-t30.S | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/arch/arm/mach-tegra/sleep-t30.S b/arch/arm/mach-tegra/sleep-t30.S index 7b188ab0604f..ece38504e315 100644 --- a/arch/arm/mach-tegra/sleep-t30.S +++ b/arch/arm/mach-tegra/sleep-t30.S @@ -831,7 +831,7 @@ tegra3_tear_down_core: /* Checking for BB-idle or Paging case */ ldr r0, [r4, #PMC_IPC_STS] tst r0, #PMC_IPC_STS_MEM_REQ | PMC_IPC_STS_MEM_REQ_SOON - movne r0, #PMC_LP_STATE_LP1BB + bne lp1bb_entry /* Write PMC_IPC_CLR[mem_sts] = 1 */ ldr r1, [r4, #PMC_IPC_CLR] @@ -843,11 +843,7 @@ tegra3_tear_down_core: bic r1, #FLOW_IPC_STS_AP2BB_MSC_STS_0 str r1, [r6, #FLOW_IPC_STS] - cmp r0, #PMC_LP_STATE_LP1BB - bne tegra3_lp0_tear_down_core - ldr r1, [r4, #PMC_IPC_SET] - orr r1, r1, #PMC_IPC_SET_MEM_STS - str r1, [r4, #PMC_IPC_SET] + b tegra3_lp0_tear_down_core /* lp1bb_entry * Set up mem_req active low to be a wake event. |