diff options
| author | Prashant Gaikwad <pgaikwad@nvidia.com> | 2013-05-30 17:25:10 +0530 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 13:16:45 -0700 |
| commit | d96f95fc3f5fb4c35e4a6a60b1002c87aba3de19 (patch) | |
| tree | 3d8eed1ea920b640cdefa9f587466512d69f2307 /arch/arm/mach-tegra/sleep-t30.S | |
| parent | 4a353580640c35aa2a9a0f66e976fbb4900fc842 (diff) | |
arm: tegra: update timing after emc register write
Need to trigger timing parameter update from software
after writing to EMC_CFG register unless there is
frequency switch. During resume from LP1 there is no
frequency switch hence update it using EMC_TIMING_CONTROL
register.
Bug 1294838
Change-Id: Id426d4e436ce033547c9e3e96a5b504b609a5c04
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/234150
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/sleep-t30.S')
| -rw-r--r-- | arch/arm/mach-tegra/sleep-t30.S | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/sleep-t30.S b/arch/arm/mach-tegra/sleep-t30.S index 8042780ad15d..c12103d90ec3 100644 --- a/arch/arm/mach-tegra/sleep-t30.S +++ b/arch/arm/mach-tegra/sleep-t30.S @@ -679,6 +679,12 @@ zcal_done: ldr r1, [r5, #0x0] str r1, [r0, #EMC_CFG] + emc_timing_update r1, r0 + + ldr r2, [r7] + add r2, r2, #5 + wait_until r2, r7, r3 + #if defined(CONFIG_ARCH_TEGRA_11x_SOC) mov32 r1, TEGRA_EMC1_BASE cmp r0, r1 |