diff options
| author | Scott Williams <scwilliams@nvidia.com> | 2011-07-25 14:55:25 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:46:58 -0800 |
| commit | d177f4e51d81f29699f6041909c26ae43a27bd76 (patch) | |
| tree | d5400a8048b6eec596bd24ee02241d1e3e200d56 /arch/arm/mach-tegra/sleep.S | |
| parent | eae868ee1d776e923b667ea2144d0aca3014a2ef (diff) | |
ARM: tegra: power: Split CPU context save and coherency exit
Separate the CPU context save and CPU coherency exit into separate
functions.
Change-Id: I7c5376677e293342b02b5bebdef6be2610522936
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R17eb40d551e797448410cf6220dfba122faa702d
Diffstat (limited to 'arch/arm/mach-tegra/sleep.S')
| -rw-r--r-- | arch/arm/mach-tegra/sleep.S | 32 |
1 files changed, 21 insertions, 11 deletions
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S index 0c15989a4cd8..77ea6b3ba363 100644 --- a/arch/arm/mach-tegra/sleep.S +++ b/arch/arm/mach-tegra/sleep.S @@ -133,6 +133,26 @@ ENDPROC(tegra_cpu_wfi) #ifdef CONFIG_PM_SLEEP /* + * tegra_cpu_exit_coherency + * + * Exits SMP coherency. + * corrupts r4-r5 + */ +ENTRY(tegra_cpu_exit_coherency) + mrc p15, 0, r4, c1, c0, 1 @ ACTLR + bic r4, r4, #(1<<6) @ exit coherency: clear ACTLR.SMP + mcr p15, 0, r4, c1, c0, 1 @ ACTLR + isb + cpu_id r4 + mov r4, r4, lsl #2 + mov r5, #0xf + mov r5, r5, lsl r4 + mov32 r4, TEGRA_ARM_PERIF_VIRT + 0xC + str r5, [r4] @ invalidate SCU tags for CPU + mov pc, lr +ENDPROC(tegra_cpu_exit_coherency) + +/* * tegra_cpu_save * * r0 = v2p @@ -161,17 +181,6 @@ ENTRY(tegra_cpu_save) mov r0, r5 mov r2, r6 mov sp, r7 - - mov r4, #0 - mcr p15, 0, r4, c1, c0, 1 @ exit coherency - isb - cpu_id r4 - mov32 r5, TEGRA_ARM_PERIF_VIRT + 0xC - mov r4, r4, lsl #2 - mov r6, #0xf - mov r6, r6, lsl r4 - str r6, [r5] @ invalidate SCU tags for CPU - mov pc, lr ENDPROC(tegra_cpu_save) @@ -184,6 +193,7 @@ ENDPROC(tegra_cpu_save) ENTRY(tegra_sleep_cpu) mov r3, lr @ set resume address to lr bl tegra_cpu_save + bl tegra_cpu_exit_coherency #ifdef CONFIG_ARCH_TEGRA_2x_SOC mov32 r1, tegra2_tear_down_cpu |