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authorScott Williams <scwilliams@nvidia.com>2011-08-03 21:38:01 -0700
committerDan Willemsen <dwillemsen@nvidia.com>2011-11-30 21:47:02 -0800
commite3e523668c9d6431ba5b2888707cd96b9d3f75b6 (patch)
tree9073d7993ac99f4bc76c12c6e75ef7e0d168565e /arch/arm/mach-tegra/sleep.S
parente0047bcef58bc524b38217c7da7feca23388b839 (diff)
ARM: tegra: power: Use uniform save/restore register set
Modify the register usage of tegra_cpu_save so that the same set of registers is saved to and restored from the stack. Change-Id: I9a0e3ce80e0e1d4b47cbb984fb732fd612bf2c16 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R89e119278eb1d8f10f3c4e1c3c3203628de37a59
Diffstat (limited to 'arch/arm/mach-tegra/sleep.S')
-rw-r--r--arch/arm/mach-tegra/sleep.S14
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
index e997b228a791..f4dac021fba4 100644
--- a/arch/arm/mach-tegra/sleep.S
+++ b/arch/arm/mach-tegra/sleep.S
@@ -167,7 +167,8 @@ ENDPROC(tegra_cpu_suspend)
*
* Input:
* r0 = v:p offset
- * r3 = resume address
+ * r12 = return to the caller of this function
+ * lr = resume address
* Output:
* r0 = v:p offset
* r7 = SP after saving the registers but before cpu_suspend, suitable
@@ -179,7 +180,7 @@ ENDPROC(tegra_cpu_suspend)
ENTRY(tegra_cpu_save)
stmfd sp!, {r4 - r11}
- stmfd sp!, {r3}
+ stmfd sp!, {lr}
/* FIXME: The next two instructions should be removed if our change to
save the diagnostic regsiter in the CPU context is accepted. */
mrc p15, 0, r4, c15, c0, 1 @ read diagnostic register
@@ -188,15 +189,14 @@ ENTRY(tegra_cpu_save)
adr r3, tegra_cpu_resume
mov r7, sp
- mov r4, lr
+ mov r4, r12
mov r5, r0
mov r6, r2
mov r1, r0
bl tegra_cpu_suspend
- mov lr, r4
mov r0, r5
mov r2, r6
- mov pc, lr
+ mov pc, r4
ENDPROC(tegra_cpu_save)
/*
@@ -206,8 +206,8 @@ ENDPROC(tegra_cpu_save)
* tegra?_tear_down_cpu
*/
ENTRY(tegra_sleep_cpu)
- mov r3, lr @ set resume address to lr
- bl tegra_cpu_save
+ mov r12, pc @ return here is via r12
+ b tegra_cpu_save
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
mov32 r1, tegra2_tear_down_cpu