diff options
| author | Bo Yan <byan@nvidia.com> | 2012-12-28 11:35:52 -0800 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 12:49:02 -0700 |
| commit | 4bbf6f882c03343d72c1f437221fe87c6eebe06f (patch) | |
| tree | c910c489898239b9ae23a18bc06d4c16d4774e20 /arch/arm/mach-tegra/sleep.S | |
| parent | 9ca5f50011ccd5a368a539f06a259246ba51ee2d (diff) | |
ARM: tegra11x: start L2 clock before enabling SMP
Do an external device read to start L2 clock, then change
SMP bit in ACTLR. The ACTLR change needs to be done immediately
after the device read is done since there are only 256 clock cycles
maximum available before the L2 clock can be gated again.
bug 1208654
bug 1195192
Change-Id: Ide1c0476d629cbea07f585013ed3b7e79a67c86e
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/187521
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bobby Meeker <bmeeker@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/sleep.S')
| -rw-r--r-- | arch/arm/mach-tegra/sleep.S | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S index 7a0233b23f77..570aeb461817 100644 --- a/arch/arm/mach-tegra/sleep.S +++ b/arch/arm/mach-tegra/sleep.S @@ -111,6 +111,12 @@ ENDPROC(tegra_pen_unlock) * corrupts r4-r5 */ ENTRY(tegra_cpu_exit_coherency) +#ifdef CONFIG_ARCH_TEGRA_11x_SOC + ldr r4, =TEGRA_CLK_RESET_VIRT + ldr r5, [r4, #70] /* BOND_OUT_L */ + tst r5, #1 + bne . +#endif exit_smp r4, r5 mov pc, lr ENDPROC(tegra_cpu_exit_coherency) |