diff options
| author | Bo Yan <byan@nvidia.com> | 2012-05-18 19:38:05 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 12:11:34 -0700 |
| commit | 7d7c3999aaa232e88fb84ce5aadb349d690dae6f (patch) | |
| tree | 6429d6d0a1c9951c5a5e95f2537a5cde24f61c80 /arch/arm/mach-tegra/sleep.S | |
| parent | 1315663a4c31e09b6565d2b8185980dab938e6b1 (diff) | |
ARM: tegra11: Update cache flush/invalidate for power gating
The field ENABLE_EXT in CSR register controls what power partition
to be gated. If it's CPU-partition power gating only, there is no
need to flush or invalidate L2 cache before/after power gating.
With this change, L2 cache is flushed/invalidated only when the
non-CPU partition is to be power gated or when rail gating is
selected.
Change-Id: I6be522de694117a058eedc9584f2157d89f99dc4
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/103476
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mark Stadler <mastadler@nvidia.com>
Reviewed-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Rebase-Id: R3108cb94a1efc64574ff58067e239bd8539e6059
Diffstat (limited to 'arch/arm/mach-tegra/sleep.S')
| -rw-r--r-- | arch/arm/mach-tegra/sleep.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S index e640e25e685f..e7b8c654ee85 100644 --- a/arch/arm/mach-tegra/sleep.S +++ b/arch/arm/mach-tegra/sleep.S @@ -162,7 +162,7 @@ ENTRY(tegra_flush_l1_cache) dsb ldmfd sp!, {r4-r5, r7, r9-r11, lr} mov pc, lr -ENDPROC(tegra_flush_l1_dcache) +ENDPROC(tegra_flush_l1_cache) #ifdef CONFIG_PM_SLEEP /* |