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authorVarun Wadekar <vwadekar@nvidia.com>2012-03-27 17:28:00 +0530
committerDan Willemsen <dwillemsen@nvidia.com>2013-09-14 00:59:57 -0700
commitc75b8af3fb59c042c3a1a0e3af508a4809305123 (patch)
tree69cf57ef005d4ef2c05f3825f29a656f3a6fd257 /arch/arm/mach-tegra/sleep.S
parent11e44d80fd411702e57b41a50e4b7350c12637cb (diff)
ARM: tegra: remove usage of USE_TEGRA_CPU_SUSPEND
Bug 934368 Change-Id: Ic9d75cbb0c324b1858b2e476e33dd4f96349bce3 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/86351 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com> Rebase-Id: Rb4fb04a26bc05a9649d17a3be8956d18998acc25
Diffstat (limited to 'arch/arm/mach-tegra/sleep.S')
-rw-r--r--arch/arm/mach-tegra/sleep.S148
1 files changed, 0 insertions, 148 deletions
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
index 1eb1d7542f25..0bbaedd6a0b8 100644
--- a/arch/arm/mach-tegra/sleep.S
+++ b/arch/arm/mach-tegra/sleep.S
@@ -122,35 +122,10 @@ ENDPROC(tegra_cpu_exit_coherency)
*/
.align L1_CACHE_SHIFT
ENTRY(tegra_cpu_resume_phys)
-#if USE_TEGRA_CPU_SUSPEND
-#ifdef CONFIG_SMP
- adr r0, tegra_phys_sleep_sp
- ALT_SMP(mrc p15, 0, r1, c0, c0, 5)
- ALT_UP(mov r1, #0)
- and r1, r1, #15
- ldr r0, [r0, r1, lsl #2] @ stack phys addr
-#else
- ldr r0, tegra_phys_sleep_sp @ stack phys addr
-#endif
- setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1 @ set SVC, irqs off
- @ load v:p, stack, resume fn
- ARM( ldmia r0!, {r1, sp, pc} )
-THUMB( ldmia r0!, {r1, r2, r3} )
-THUMB( mov sp, r2 )
-THUMB( bx r3 )
-#else
/* Use the standard cpu_resume. */
b cpu_resume
-#endif
ENDPROC(tegra_cpu_resume_phys)
-#if USE_TEGRA_CPU_SUSPEND
-tegra_phys_sleep_sp:
- .rept 4
- .long 0 @ preserve stack phys ptr here
- .endr
-#endif
-
/*
* tegra_cpu_suspend
*
@@ -169,109 +144,6 @@ tegra_phys_sleep_sp:
ENTRY(tegra_cpu_suspend)
mov r9, lr
adr lr, tegra_cpu_resume
-#if USE_TEGRA_CPU_SUSPEND
- stmfd sp!, {r4 - r11, lr}
-#ifdef MULTI_CPU
- mov32 r10, processor
- ldr r5, [r10, #CPU_SLEEP_SIZE] @ size of CPU sleep state
- ldr ip, [r10, #CPU_DO_RESUME] @ virtual resume function
-#else
- mov32 r5, cpu_suspend_size
- mov32 ip, cpu_do_resume
-#endif
- mov r6, sp @ current virtual SP
- sub sp, sp, r5 @ allocate CPU state on stack
- mov r0, sp @ save pointer to CPU save block
- add ip, ip, r1 @ convert resume fn to phys
- stmfd sp!, {r1, r6, ip} @ save v:p, virt SP, phys resume fn
-
-#ifdef MULTI_CPU
- mov lr, pc
- ldr pc, [r10, #CPU_DO_SUSPEND] @ save CPU state
-#else
- bl cpu_do_suspend
-#endif
- dsb
-
- /* Disable the data cache */
- mrc p15, 0, r10, c1, c0, 0
- bic r10, r10, #CR_C
- dsb
- mcr p15, 0, r10, c1, c0, 0
- isb
-
- /* Flush data cache */
-#ifdef MULTI_CACHE
- mov32 r10, cpu_cache
- mov lr, pc
- ldr pc, [r10, #CACHE_FLUSH_KERN_ALL]
-#else
- bl __cpuc_flush_kern_all
-#endif
-#ifdef CONFIG_CACHE_L2X0
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
- cpu_id r2
- cmp r2, #0
- bne no_l2_sync
-#endif
- /* Issue a PL310 cache sync operation */
- dsb
- mov32 r2, TEGRA_PL310_VIRT
- movw r1, 0x730 @ cache sync
- add r2, r2, r1
- mov r1, #0
- str r1, [r2]
-#endif
-
-no_l2_sync:
- /* Invalidate the TLBs & BTAC */
- mov r1, #0
- mcr p15, 0, r1, c8, c3, 0 @ invalidate shared TLBs
- mcr p15, 0, r1, c7, c1, 6 @ invalidate shared BTAC
- dsb
- isb
-
- /* Turn off SMP coherency */
- exit_smp r1, r2
-
- /* Convert SP from virtual to physical address. */
- movw r1, #0xFFF
- bic r2, sp, r1 @ VA & 0xFFFFF000
- mcr p15, 0, r2, c7, c8, 0 @ V2PPRPC
- mrc p15, 0, r2, c7, c4, 0 @ PAR
- bic r2, r2, r1 @ PA & 0xFFFFF000
- and r0, sp, r1 @ VA & 0x00000FFF
- orr r2, r0, r2 @ (PA & 0xFFFFF000) | (VA & 0x00000FFF)
-
- mov32 r3, tegra_phys_sleep_sp @ per-CPU phys SP save area
-
-#ifdef CONFIG_SMP
- ALT_SMP(mrc p15, 0, lr, c0, c0, 5)
- ALT_UP(mov lr, #0)
- and lr, lr, #15
-#else
- mov lr, #0
-#endif
-
- /* Save the normal PRRR value */
- mrc p15, 0, r0, c10, c2, 0 @ PRRR
-
- /* Override all remappings to strongly ordered */
- mov r1, #0
- mcr p15, 0, r1, c10, c2, 0 @ PRRR
- mcr p15, 0, r1, c8, c7, 0 @ invalidate local TLBs
- dsb
- isb
-
- /* Save the physical stack pointer */
- str r2, [r3, lr, lsl #2] @ save phys SP
-
- /* Restore the regular remappings */
- mcr p15, 0, r0, c10, c2, 0 @ PRRR
- mcr p15, 0, r1, c8, c7, 0 @ invalidate local TLBs
- dsb
- isb
-#else
/* Use the standard cpu_suspend. */
adr r3, BSYM(tegra_finish_suspend)
b __cpu_suspend
@@ -279,7 +151,6 @@ no_l2_sync:
tegra_finish_suspend:
/* Turn off SMP coherency */
exit_smp r1, r6
-#endif
mov pc, r9
ENDPROC(tegra_cpu_suspend)
@@ -303,18 +174,6 @@ ENTRY(tegra_cpu_save)
mov r7, sp @ SP after reg save, before suspend
-#if USE_TEGRA_CPU_SUSPEND
- cpu_id r4
- mov32 r5, tegra_cpu_context @ address of non-cacheable context page
- ldr r5, [r5] @ non-cacheable context save area
- mov r6, #0x400 @ size of one CPU context stack area
- add r4, r4, #1
- smlabb sp, r6, r4, r5 @ context area for this CPU
- push_stack_token r4 @ debug check word
- stmfd sp!, {r7} @ save the real stack pointer
- push_stack_token r4 @ debug check word
-#endif
-
mov r4, r12
mov r8, r0
mov r11, r2
@@ -360,13 +219,6 @@ tegra_cpu_resume:
dsb
isb
-#if USE_TEGRA_CPU_SUSPEND
- pop_stack_token r4, r5 @ check stack debug token
- ldmfd sp!, {r0} @ get the real stack pointer
- pop_stack_token r4, r5 @ check stack debug token
- mov sp, r0 @ switch to the real stack pointer
-#endif
-
bl cpu_init
pop_ctx_regs r1, r2 @ restore context registers