diff options
| author | Amit Kamath <akamath@nvidia.com> | 2013-01-29 15:39:58 +0530 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 12:57:32 -0700 |
| commit | cc4f711fcae5ea325911632f960611d396f98cfb (patch) | |
| tree | f85a23533f57286b2bce1f177f67b2e4583bd2b8 /arch/arm/mach-tegra/sleep.S | |
| parent | 70d84f612026a34e08419428cb21737994de1b63 (diff) | |
ARM: tegra: Add barriers after cache operations
memory and instruction barriers are needed after the tlb is
invalidated and BTAC is flushed as per ARM TRM. Without this
there is a invalid page translation in some cases.
Bug 1189280
Reviewed-on: http://git-master/r/195070
(cherry picked from commit 997c54686349728cdf54cfeae96b5f4078ccb436)
Change-Id: I85e297ffd9245c5066f656bbb70ea257b8b3b317
Signed-off-by: Amit Kamath <akamath@nvidia.com>
Reviewed-on: http://git-master/r/199867
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Sarvesh Satavalekar <ssatavalekar@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/sleep.S')
| -rw-r--r-- | arch/arm/mach-tegra/sleep.S | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S index 48d2be0a8bee..b634d0e75927 100644 --- a/arch/arm/mach-tegra/sleep.S +++ b/arch/arm/mach-tegra/sleep.S @@ -256,10 +256,11 @@ ENTRY(tegra_turn_off_mmu) mcr p15, 0, r3, c2, c0, 0 @ TTB 0 isb - mov r2, #0 mcr p15, 0, r2, c8, c3, 0 @ invalidate TLB mcr p15, 0, r2, c7, c5, 6 @ flush BTAC mcr p15, 0, r2, c7, c5, 0 @ flush instruction cache + dsb + isb mov32 r3, tegra_shut_off_mmu add r3, r3, r0 |