diff options
| author | Scott Williams <scwilliams@nvidia.com> | 2011-08-03 17:33:37 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:47:01 -0800 |
| commit | 68437fa5d8cf810c58643b364f906cb7ae29561f (patch) | |
| tree | eb7c4196a9858acd34913a2e9f45d851e422518a /arch/arm/mach-tegra/sleep.h | |
| parent | a0f57a8931b76c3f63299b3715b3629a613c1bf9 (diff) | |
ARM: tegra: power: Add SMP coherency exit macro
Define the SMP coherency exit code as a macro to allow it to be
inlined in assembly code that needs to control its register usage.
Change-Id: If5bd01241a92eb471cf59b4fc8445934fd4932b1
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: R921ed4d46431115d164f73bacac16a68a9d32b0a
Diffstat (limited to 'arch/arm/mach-tegra/sleep.h')
| -rw-r--r-- | arch/arm/mach-tegra/sleep.h | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h index a6f6b1740009..02ab870edbbe 100644 --- a/arch/arm/mach-tegra/sleep.h +++ b/arch/arm/mach-tegra/sleep.h @@ -74,8 +74,26 @@ #endif #define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS + IO_PPSB_VIRT) +#define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS + IO_CPU_VIRT) + +#ifdef __ASSEMBLY__ + +/* Macro to exit SMP coherency. */ +.macro exit_smp, tmp1, tmp2 + mrc p15, 0, \tmp1, c1, c0, 1 @ ACTLR + bic \tmp1, \tmp1, #(1<<6) @ clear ACTLR.SMP + mcr p15, 0, \tmp1, c1, c0, 1 @ ACTLR + isb + cpu_id \tmp1 + mov \tmp1, \tmp1, lsl #2 + mov \tmp2, #0xf + mov \tmp2, \tmp2, lsl \tmp1 + mov32 \tmp1, TEGRA_ARM_PERIF_VIRT + 0xC + str \tmp2, [\tmp1] @ invalidate SCU tags for CPU + dsb +.endm -#ifndef __ASSEMBLY__ +#else #define FLOW_CTRL_HALT_CPU(cpu) (IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + \ ((cpu) ? (FLOW_CTRL_HALT_CPU1_EVENTS + 8 * ((cpu) - 1)) : \ |