diff options
| author | Scott Williams <scwilliams@nvidia.com> | 2011-07-22 16:34:15 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:46:53 -0800 |
| commit | 699d5f11a7890392338ca9b67bf92b25783c958f (patch) | |
| tree | 918b918111fdb35e6a508792d96e60c9a04a1222 /arch/arm/mach-tegra/sleep.h | |
| parent | 5ea574a7b8daac998ec52802157c72d94e652dbb (diff) | |
ARM: tegra: Consolidate flow control registers
Change-Id: I07ffcffafcf47fd7539b22d4829712e041293bf3
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
DW: Split into logical changes
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R34a7800e24254d54b499411652d59421be703619
Diffstat (limited to 'arch/arm/mach-tegra/sleep.h')
| -rw-r--r-- | arch/arm/mach-tegra/sleep.h | 46 |
1 files changed, 39 insertions, 7 deletions
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h index 2332e6f2c574..78325f49b85e 100644 --- a/arch/arm/mach-tegra/sleep.h +++ b/arch/arm/mach-tegra/sleep.h @@ -39,18 +39,50 @@ #define CPU_RESETTABLE_SOON 1 #define CPU_NOT_RESETTABLE 0 -#define FLOW_CTRL_WAITEVENT (2 << 29) -#define FLOW_CTRL_WAIT_FOR_INTERRUPT (4 << 29) -#define FLOW_CTRL_JTAG_RESUME (1 << 28) -#define FLOW_CTRL_HALT_CPU_IRQ (1 << 10) -#define FLOW_CTRL_HALT_CPU_FIQ (1 << 8) +#define FLOW_CTRL_HALT_CPU0_EVENTS 0x0 +#define FLOW_CTRL_WAITEVENT (2 << 29) +#define FLOW_CTRL_WAIT_FOR_INTERRUPT (4 << 29) +#define FLOW_CTRL_JTAG_RESUME (1 << 28) +#define FLOW_CTRL_HALT_CPU_IRQ (1 << 10) +#define FLOW_CTRL_HALT_CPU_FIQ (1 << 8) +#define FLOW_CTRL_CPU0_CSR 0x8 +#define FLOW_CTRL_CSR_INTR_FLAG (1 << 15) +#define FLOW_CTRL_CSR_EVENT_FLAG (1 << 14) +#define FLOW_CTRL_CSR_ENABLE (1 << 0) +#define FLOW_CTRL_HALT_CPU1_EVENTS 0x14 +#define FLOW_CTRL_CPU1_CSR 0x18 -#define FLOW_CTRL_CSR_INTR_FLAG (1<<15) -#define FLOW_CTRL_CSR_EVENT_FLAG (1<<14) +#ifdef CONFIG_ARCH_TEGRA_2x_SOC +#define FLOW_CTRL_CSR_WFE_CPU0 (1 << 4) +#define FLOW_CTRL_CSR_WFE_BITMAP (3 << 4) +#define FLOW_CTRL_CSR_WFI_BITMAP 0 +#else +#define FLOW_CTRL_CSR_WFE_BITMAP (0xF << 4) +#define FLOW_CTRL_CSR_WFI_CPU0 (1 << 8) +#define FLOW_CTRL_CSR_WFI_BITMAP (0xF << 8) +#endif #define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS + IO_PPSB_VIRT) #ifndef __ASSEMBLY__ + +#define FLOW_CTRL_HALT_CPU(cpu) (IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + \ + ((cpu) ? (FLOW_CTRL_HALT_CPU1_EVENTS + 8 * ((cpu) - 1)) : \ + FLOW_CTRL_HALT_CPU0_EVENTS)) + +#define FLOW_CTRL_CPU_CSR(cpu) (IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + \ + ((cpu) ? (FLOW_CTRL_CPU1_CSR + 8 * ((cpu) - 1)) : \ + FLOW_CTRL_CPU0_CSR)) + +static inline void flowctrl_writel(unsigned long val, void __iomem *addr) +{ + writel(val, addr); +#ifdef CONFIG_ARCH_TEGRA_2x_SOC + wmb(); +#endif + (void)__raw_readl(addr); +} + void tegra_pen_lock(void); void tegra_pen_unlock(void); void tegra_cpu_wfi(void); |