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authorManoj Chourasia <mchourasia@nvidia.com>2011-11-24 21:08:22 +0530
committerDan Willemsen <dwillemsen@nvidia.com>2011-11-30 21:50:22 -0800
commitdb543c71362406d616fad89f11dff88e80ea71dd (patch)
tree99ba893b6fbc431eecd34e4026c74da4c1dc17ab /arch/arm/mach-tegra/tegra2_clocks.c
parent4f89825ef7413b378d07033fce78b7761c428097 (diff)
tegra: NOR: Allow mapping NOR aperture and clocks.
Renamed client driver for nor clock from "nor" to "tegra-nor". Add NOR flash aperature as valid address range in ioremap. Reviewed-on: http://git-master/r/44746 (cherry picked from commit 151b678580c43fa53bacd22f7f3d847d3eac3f6d) Change-Id: I61bcb316f3e9f757f24260bc24e2c4378f8e3326 Signed-off-by: Manoj Chourasia <mchourasia@nvidia.com> Reviewed-on: http://git-master/r/66706 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Rebase-Id: R2e2a9a1ee7162a8073758150e56d5c1f8aa1f2fd
Diffstat (limited to 'arch/arm/mach-tegra/tegra2_clocks.c')
-rw-r--r--arch/arm/mach-tegra/tegra2_clocks.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index 7686b3c367c8..bcf40979ddbd 100644
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -2402,7 +2402,7 @@ struct clk tegra_list_periph_clks[] = {
/* FIXME: what is la? */
PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 0x31E, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 0x31E, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("nor", "nor", NULL, 42, 0x1d0, 0x31E, 92000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
+ PERIPH_CLK("nor", "tegra-nor", NULL, 42, 0x1d0, 0x31E, 92000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, 0x31E, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), /* scales with voltage */
PERIPH_CLK("i2c1", "tegra-i2c.0", NULL, 12, 0x124, 0x31E, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
PERIPH_CLK("i2c2", "tegra-i2c.1", NULL, 54, 0x198, 0x31E, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16 | PERIPH_ON_APB),