diff options
| author | Colin Cross <ccross@android.com> | 2011-01-10 18:39:43 -0800 |
|---|---|---|
| committer | Colin Cross <ccross@android.com> | 2011-01-10 18:56:11 -0800 |
| commit | 08da711a7475bebdca5eec2d8b51751f380067a2 (patch) | |
| tree | cba222c993df3799c06e6a6e188cc66b56ee5492 /arch/arm/mach-tegra/tegra2_clocks.c | |
| parent | f7120584faebeb1e3d907f4e18f61c3285db1f78 (diff) | |
ARM: tegra: clock: Save and restore plld, plls, and pllu in suspend
HDMI was not working after LP0 because the plld were being reset
during suspend. plls and pllu were also not being saved. Add
all three to tegra_clk_suspend.
The lock time for plld is 1000 us, so increase the delay after
setting the PLLs.
Add a BUG_ON to ensure the size of the suspend context area is
correct.
Originally fixed by Mayuresh Kulkarni.
Original-author: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Change-Id: I50a3e994c6e3cab5989aa7a8e26e7a2eb66b6dfb
Signed-off-by: Colin Cross <ccross@android.com>
Diffstat (limited to 'arch/arm/mach-tegra/tegra2_clocks.c')
| -rw-r--r-- | arch/arm/mach-tegra/tegra2_clocks.c | 18 |
1 files changed, 16 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c index d3e17c1621f7..3f2eccc2fa92 100644 --- a/arch/arm/mach-tegra/tegra2_clocks.c +++ b/arch/arm/mach-tegra/tegra2_clocks.c @@ -2134,7 +2134,7 @@ void __init tegra2_init_clocks(void) #ifdef CONFIG_PM static u32 clk_rst_suspend[RST_DEVICES_NUM + CLK_OUT_ENB_NUM + - PERIPH_CLK_SOURCE_NUM + 15]; + PERIPH_CLK_SOURCE_NUM + 21]; void tegra_clk_suspend(void) { @@ -2146,6 +2146,12 @@ void tegra_clk_suspend(void) *ctx++ = clk_readl(tegra_pll_c.reg + PLL_MISC(&tegra_pll_c)); *ctx++ = clk_readl(tegra_pll_a.reg + PLL_BASE); *ctx++ = clk_readl(tegra_pll_a.reg + PLL_MISC(&tegra_pll_a)); + *ctx++ = clk_readl(tegra_pll_s.reg + PLL_BASE); + *ctx++ = clk_readl(tegra_pll_s.reg + PLL_MISC(&tegra_pll_s)); + *ctx++ = clk_readl(tegra_pll_d.reg + PLL_BASE); + *ctx++ = clk_readl(tegra_pll_d.reg + PLL_MISC(&tegra_pll_d)); + *ctx++ = clk_readl(tegra_pll_u.reg + PLL_BASE); + *ctx++ = clk_readl(tegra_pll_u.reg + PLL_MISC(&tegra_pll_u)); *ctx++ = clk_readl(tegra_pll_m_out1.reg); *ctx++ = clk_readl(tegra_pll_a_out0.reg); @@ -2175,6 +2181,8 @@ void tegra_clk_suspend(void) *ctx++ = clk_readl(MISC_CLK_ENB); *ctx++ = clk_readl(CLK_MASK_ARM); + + BUG_ON(ctx - clk_rst_suspend != ARRAY_SIZE(clk_rst_suspend)); } void tegra_clk_resume(void) @@ -2191,7 +2199,13 @@ void tegra_clk_resume(void) clk_writel(*ctx++, tegra_pll_c.reg + PLL_MISC(&tegra_pll_c)); clk_writel(*ctx++, tegra_pll_a.reg + PLL_BASE); clk_writel(*ctx++, tegra_pll_a.reg + PLL_MISC(&tegra_pll_a)); - udelay(300); + clk_writel(*ctx++, tegra_pll_s.reg + PLL_BASE); + clk_writel(*ctx++, tegra_pll_s.reg + PLL_MISC(&tegra_pll_s)); + clk_writel(*ctx++, tegra_pll_d.reg + PLL_BASE); + clk_writel(*ctx++, tegra_pll_d.reg + PLL_MISC(&tegra_pll_d)); + clk_writel(*ctx++, tegra_pll_u.reg + PLL_BASE); + clk_writel(*ctx++, tegra_pll_u.reg + PLL_MISC(&tegra_pll_u)); + udelay(1000); clk_writel(*ctx++, tegra_pll_m_out1.reg); clk_writel(*ctx++, tegra_pll_a_out0.reg); |