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| author | Sumit Bhattacharya <sumitb@nvidia.com> | 2011-02-21 16:05:21 +0530 |
|---|---|---|
| committer | Varun Colbert <vcolbert@nvidia.com> | 2011-02-22 18:09:04 -0800 |
| commit | e74baeb904c579cc8fff2d7fa12cd4a6d83a2708 (patch) | |
| tree | c4e4f6073eb6f2fcfd993e85a87dea1f24d895a3 /arch/arm/mach-tegra/tegra2_i2s.c | |
| parent | 98d54eb3423b961039d7db01889f5c57d9128d76 (diff) | |
[ARM] tegra: i2s and das suspend/resume
Add APIs in das driver to get and set das register values.
ALSA driver will be using these APIs to cache das register
values during system suspend resume.
In i2s register get/set APIs caching few more registers.
Bug 789967
Bug 792879
Change-Id: Iaa4487cb003d2f75d5c54f450f17833c7af96cf2
Reviewed-on: http://git-master/r/20291
Tested-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-by: Vijay Mali <vmali@nvidia.com>
Reviewed-by: Ravindra Lokhande <rlokhande@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/tegra2_i2s.c')
| -rw-r--r-- | arch/arm/mach-tegra/tegra2_i2s.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/tegra2_i2s.c b/arch/arm/mach-tegra/tegra2_i2s.c index de50df917048..7147b0b38efb 100644 --- a/arch/arm/mach-tegra/tegra2_i2s.c +++ b/arch/arm/mach-tegra/tegra2_i2s.c @@ -78,6 +78,10 @@ void i2s_get_all_regs(int ifc, struct i2s_runtime_data* ird) ird->i2s_status_0 = i2s_readl(ifc, I2S_I2S_STATUS_0); ird->i2s_timing_0 = i2s_readl(ifc, I2S_I2S_TIMING_0); ird->i2s__fifo_scr_0 = i2s_readl(ifc, I2S_I2S_FIFO_SCR_0); + ird->i2s_pcm_ctrl_0 = i2s_readl(ifc, I2S_I2S_PCM_CTRL_0); + ird->i2s_nw_ctrl_0 = i2s_readl(ifc, I2S_I2S_NW_CTRL_0); + ird->i2s_tdm_ctrl_0 = i2s_readl(ifc, I2S_I2S_TDM_CTRL_0); + ird->i2s_tdm_tx_rx_ctrl_0 = i2s_readl(ifc, I2S_I2S_TDM_TX_RX_CTRL_0); ird->i2s_fifo1_0 = i2s_readl(ifc, I2S_I2S_FIFO1_0); ird->i2s_fifo2_0 = i2s_readl(ifc, I2S_I2S_FIFO2_0); } @@ -89,6 +93,10 @@ void i2s_set_all_regs(int ifc, struct i2s_runtime_data* ird) i2s_writel(ifc, ird->i2s_status_0, I2S_I2S_STATUS_0); i2s_writel(ifc, ird->i2s_timing_0, I2S_I2S_TIMING_0); i2s_writel(ifc, ird->i2s__fifo_scr_0, I2S_I2S_FIFO_SCR_0); + i2s_writel(ifc, ird->i2s_pcm_ctrl_0, I2S_I2S_PCM_CTRL_0); + i2s_writel(ifc, ird->i2s_nw_ctrl_0, I2S_I2S_NW_CTRL_0); + i2s_writel(ifc, ird->i2s_tdm_ctrl_0, I2S_I2S_TDM_CTRL_0); + i2s_writel(ifc, ird->i2s_tdm_tx_rx_ctrl_0, I2S_I2S_TDM_TX_RX_CTRL_0); i2s_writel(ifc, ird->i2s_fifo1_0, I2S_I2S_FIFO1_0); i2s_writel(ifc, ird->i2s_fifo2_0, I2S_I2S_FIFO2_0); } |