diff options
| author | Rahul Prabhakar <rahulp@nvidia.com> | 2011-09-13 15:40:45 -0700 |
|---|---|---|
| committer | Frank Bourgeois <fbourgeois@nvidia.com> | 2011-09-21 18:03:43 -0700 |
| commit | 7742e7756c0637ae5378e394ca03978826e31a78 (patch) | |
| tree | 8cc31ae92f8e004adfb290ba035b4887bed088c9 /arch/arm/mach-tegra/tegra2_save.S | |
| parent | 47a4ffb6af7aec974ecb463ba7eb068422b3c3d4 (diff) | |
ARM: tegra: TrustedLogic drop 32055tegra-12r9-android-3.2
The WARs checked into 12r7: disable LP0/LP1 and slave LP2, and force
maxcpus to 1 aren't needed when used with the newer tf_include.h from
this TL drop.
bug 868906
bug 870224
bug 877339
Change-Id: Ic3002b1d5fa09e8171c0d43bf6978ae96e51daf8
Reviewed-on: http://git-master/r/53324
Reviewed-by: Rahul Prabhakar <rahulp@nvidia.com>
Tested-by: Rahul Prabhakar <rahulp@nvidia.com>
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Reviewed-by: Jonathan White <jwhite@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/tegra2_save.S')
| -rw-r--r-- | arch/arm/mach-tegra/tegra2_save.S | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/tegra2_save.S b/arch/arm/mach-tegra/tegra2_save.S index 3c0de77d21ec..cb76786ee1f3 100644 --- a/arch/arm/mach-tegra/tegra2_save.S +++ b/arch/arm/mach-tegra/tegra2_save.S @@ -183,13 +183,17 @@ __tegra_lp1_reset: /* the CPU and system bus are running at 32KHz and executing from * IRAM when this code is executed; immediately switch to CLKM and * enable PLLP. */ + mov32 r0, TEGRA_CLK_RESET_BASE +#ifndef CONFIG_TRUSTED_FOUNDATIONS + /* secure code handles 32KHz to CLKM/OSC clock switch */ mov r1, #(1<<28) str r1, [r0, #CLK_RESET_SCLK_BURST] str r1, [r0, #CLK_RESET_CCLK_BURST] mov r1, #0 str r1, [r0, #CLK_RESET_SCLK_DIVIDER] str r1, [r0, #CLK_RESET_CCLK_DIVIDER] +#endif ldr r1, [r0, #CLK_RESET_PLLM_BASE] tst r1, #(1<<30) |