diff options
| author | Alex Frid <afrid@nvidia.com> | 2011-04-05 20:24:36 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:42:31 -0800 |
| commit | bc72e03d7333f415488e32a9b9f264a9777649f0 (patch) | |
| tree | 9bb71f78afd138578e015a8310a5a572c614c1e8 /arch/arm/mach-tegra/tegra3_emc.c | |
| parent | 44d215b19e2a90005cbf7c03586f30b712883a5e (diff) | |
ARM: tegra: power: Re-initialize Tegra3 EMC after LP0
Since EMC frequency is not restored after exit from LP0, re-initialize
EMC clock with the new warm boot configuration, and make sure that the
1st after LP0 clock change does not use stale timing cache.
Skip Tegra2 specific EMC restoration on Tegra3 platforms.
Original-Change-Id: I4be0d3b839e871151c3c2158a002a0c763de34c2
Reviewed-on: http://git-master/r/26807
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I2ffeb64d96a425966d258d0479b3561c4a6eb406
Rebase-Id: Rb3fcd60c0c674e10d41d4cdc4d8e53a6e124a5bf
Diffstat (limited to 'arch/arm/mach-tegra/tegra3_emc.c')
| -rw-r--r-- | arch/arm/mach-tegra/tegra3_emc.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/tegra3_emc.c b/arch/arm/mach-tegra/tegra3_emc.c index 2335d90504b8..d4ee7d9f3af2 100644 --- a/arch/arm/mach-tegra/tegra3_emc.c +++ b/arch/arm/mach-tegra/tegra3_emc.c @@ -181,6 +181,7 @@ enum { static struct clk_mux_sel tegra_emc_clk_sel[TEGRA_EMC_TABLE_MAX_SIZE]; static int emc_last_sel; static struct tegra_emc_table start_timing; +static bool emc_timing_in_sync; static const struct tegra_emc_table *tegra_emc_table; static int tegra_emc_table_size; @@ -606,7 +607,7 @@ int tegra_emc_set_rate(unsigned long rate) if (i >= tegra_emc_table_size) return -EINVAL; - if (!emc_stats.clkchange_count) { + if (!emc_timing_in_sync) { /* can not assume that boot timing matches dfs table even if boot frequency matches one of the table nodes */ emc_get_timing(&start_timing); @@ -617,6 +618,7 @@ int tegra_emc_set_rate(unsigned long rate) clk_setting = tegra_emc_clk_sel[i].value; emc_set_clock(&tegra_emc_table[i], last_timing, clk_setting); + emc_timing_in_sync = true; emc_last_stats_update(i); pr_debug("%s: rate %lu setting 0x%x\n", __func__, rate, clk_setting); @@ -781,6 +783,11 @@ void tegra_init_emc(const struct tegra_emc_table *table, int table_size) tegra_emc_table = table; } +void tegra_emc_timing_invalidate(void) +{ + emc_timing_in_sync = false; +} + #ifdef CONFIG_DEBUG_FS static struct dentry *emc_debugfs_root; |